drivers: ssp: start with xtal clock on ssp ver >= 2.0
This patch will save configured link clock and ensure ssp starts with xtal clock if ssp ver >= 2.0 Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
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2 changed files with 19 additions and 0 deletions
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@ -1936,6 +1936,7 @@ static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, s
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struct ssp_intel_ext_ctl *ext;
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#if SSP_IP_VER >= SSP_IP_VER_1_5
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struct ssp_intel_link_ctl *link;
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struct dai_intel_ssp_plat_data *ssp = dai_get_plat_data(dp);
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#endif
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for (i = 0; i < aux_len; i += hop) {
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@ -1989,6 +1990,7 @@ static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, s
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I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
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I2SLCTL_OFFSET);
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#elif SSP_IP_VER > SSP_IP_VER_1_5
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ssp->link_clock = link->clock_source;
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sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) &
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~I2CLCTL_MLCS(0x7)) |
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I2CLCTL_MLCS(link->clock_source),
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@ -2551,6 +2553,14 @@ static void ssp_acquire_ip(struct dai_intel_ssp *dp)
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/* Disable dynamic clock gating before touching any register */
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dai_ssp_pm_runtime_dis_ssp_clk_gating(dp, ssp->ssp_index);
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#if SSP_IP_VER >= SSP_IP_VER_2_0
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/* Switch to selected clock source */
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sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) &
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~I2CLCTL_MLCS(0x7)) |
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I2CLCTL_MLCS(ssp->link_clock),
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dai_i2svss_base(dp) + I2SLCTL_OFFSET);
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#endif
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}
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}
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@ -2576,6 +2586,14 @@ static void ssp_release_ip(struct dai_intel_ssp *dp)
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dai_ssp_post_stop(dp);
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#if SSP_IP_VER >= SSP_IP_VER_2_0
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/* Restore default XTAL clock source */
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sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) &
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~I2CLCTL_MLCS(0x7)) |
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I2CLCTL_MLCS(DAI_INTEL_SSP_CLOCK_XTAL_OSCILLATOR),
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dai_i2svss_base(dp) + I2SLCTL_OFFSET);
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#endif
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dai_ssp_pm_runtime_en_ssp_clk_gating(dp, ssp->ssp_index);
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dai_ssp_mclk_disable_unprepare(dp);
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@ -137,6 +137,7 @@ struct dai_intel_ssp_plat_data {
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#if SSP_IP_VER > SSP_IP_VER_1_5
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uint32_t hdamlssp_base;
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uint32_t i2svss_base;
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uint32_t link_clock;
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#endif
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int irq;
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const char *irq_name;
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