soc: nordic: nrf54l: Add nrf54l09 enga SoC
Add nrf54l09 EngA SoC in soc, dts and hal_nordic. Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This commit is contained in:
Krzysztof Chruściński
Benjamin Cabé
parent
d5637ec374
commit
b0afa1e571
9 changed files with 2156 additions and 2 deletions
136
dts/arm/nordic/nrf54l09_enga_cpuapp.dtsi
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136
dts/arm/nordic/nrf54l09_enga_cpuapp.dtsi
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@ -0,0 +1,136 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nordic/nrf54l09.dtsi>
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cpu: &cpuapp {};
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systick: &cpuapp_systick {};
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nvic: &cpuapp_nvic {};
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/delete-node/ &cpuflpr;
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/delete-node/ &cpuflpr_rram;
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/delete-node/ &cpuflpr_sram;
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/delete-node/ &cpuflpr_clic;
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/ {
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chosen {
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zephyr,bt-hci = &bt_hci_controller;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&cpuapp_nvic>;
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ranges;
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};
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psa_rng: psa-rng {
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compatible = "zephyr,psa-crypto-rng";
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status = "disabled";
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};
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};
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&bt_hci_controller {
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status = "okay";
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};
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&cpuflpr_vpr {
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cpuapp_vevif_rx: mailbox@1 {
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compatible = "nordic,nrf-vevif-event-rx";
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reg = <0x1 0x1000>;
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status = "disabled";
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interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>;
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#mbox-cells = <1>;
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nordic,events = <1>;
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nordic,events-mask = <0x00100000>;
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};
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cpuapp_vevif_tx: mailbox@0 {
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compatible = "nordic,nrf-vevif-task-tx";
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reg = <0x0 0x1000>;
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#mbox-cells = <1>;
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nordic,tasks = <7>;
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nordic,tasks-mask = <0x007f0000>;
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status = "disabled";
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};
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};
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&cpuapp_ppb {
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compatible = "simple-bus";
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ranges;
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};
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&grtc {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>,
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#else
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interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>,
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#endif
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<229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */
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};
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&gpiote20 {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
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#else
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interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>;
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#endif
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};
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&gpiote30 {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
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#else
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interrupts = <269 NRF_DEFAULT_IRQ_PRIORITY>;
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#endif
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};
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&dppic00 {
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status = "okay";
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};
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&dppic10 {
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status = "okay";
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};
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&dppic20 {
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status = "okay";
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};
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&dppic30 {
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status = "okay";
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};
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&ppib00 {
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status = "okay";
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};
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&ppib01 {
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status = "okay";
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};
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&ppib10 {
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status = "okay";
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};
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&ppib11 {
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status = "okay";
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};
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&ppib20 {
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status = "okay";
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};
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&ppib21 {
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status = "okay";
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};
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&ppib22 {
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status = "okay";
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};
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&ppib30 {
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status = "okay";
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};
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615
dts/common/nordic/nrf54l09.dtsi
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615
dts/common/nordic/nrf54l09.dtsi
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <nordic/nrf_common.dtsi>
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#include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
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#include <zephyr/dt-bindings/regulator/nrf5x.h>
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/delete-node/ &sw_pwm;
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/* Domain IDs. Can be used to specify channel links in IPCT nodes. */
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#define NRF_DOMAIN_ID_APPLICATION 0
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#define NRF_DOMAIN_ID_FLPR 1
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpuapp: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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device_type = "cpu";
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clock-frequency = <DT_FREQ_M(64)>;
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#address-cells = <1>;
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#size-cells = <1>;
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itm: itm@e0000000 {
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compatible = "arm,armv8m-itm";
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reg = <0xe0000000 0x1000>;
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swo-ref-frequency = <DT_FREQ_M(128)>;
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};
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};
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cpuflpr: cpu@1 {
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compatible = "nordic,vpr";
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reg = <1>;
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device_type = "cpu";
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clock-frequency = <DT_FREQ_M(128)>;
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riscv,isa = "rv32emc";
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nordic,bus-width = <32>;
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};
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};
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clocks {
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lfxo: lfxo {
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compatible = "nordic,nrf-lfxo";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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hfxo: hfxo {
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compatible = "nordic,nrf-hfxo";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(32)>;
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};
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hfpll: hfpll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(128)>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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/* intentionally empty because UICR is hardware fixed to Secure */
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#else
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uicr: uicr@ffd000 {
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compatible = "nordic,nrf-uicr";
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reg = <0xffd000 0x1000>;
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};
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#endif
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ficr: ficr@ffc000 {
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compatible = "nordic,nrf-ficr";
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reg = <0xffc000 0x1000>;
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#nordic,ficr-cells = <1>;
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};
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cpuapp_sram: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(144)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(144)>;
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compatible = "mmio-sram";
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#address-cells = <1>;
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#size-cells = <1>;
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};
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cpuflpr_sram: memory@20024000 {
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compatible = "mmio-sram";
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reg = <0x20024000 DT_SIZE_K(48)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x20024000 DT_SIZE_K(48)>;
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};
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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global_peripherals: peripheral@40000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x40000000 0x10000000>;
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#else
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global_peripherals: peripheral@50000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x50000000 0x10000000>;
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#endif
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dppic00: dppic@42000 {
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compatible = "nordic,nrf-dppic";
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reg = <0x42000 0x808>;
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status = "disabled";
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};
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ppib00: ppib@44000 {
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compatible = "nordic,nrf-ppib";
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reg = <0x44000 0x1000>;
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status = "disabled";
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};
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ppib01: ppib@45000 {
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compatible = "nordic,nrf-ppib";
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reg = <0x45000 0x1000>;
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status = "disabled";
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};
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cpuflpr_vpr: vpr@4c000 {
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compatible = "nordic,nrf-vpr-coprocessor";
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reg = <0x4c000 0x1000>;
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ranges = <0x0 0x4c000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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cpuflpr_clic: interrupt-controller@f0000000 {
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compatible = "nordic,nrf-clic";
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reg = <0xf0000000 0x1780>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#address-cells = <1>;
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status = "disabled";
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};
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};
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timer00: timer@55000 {
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compatible = "nordic,nrf-timer";
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status = "disabled";
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reg = <0x55000 0x1000>;
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cc-num = <6>;
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max-bit-width = <32>;
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interrupts = <85 NRF_DEFAULT_IRQ_PRIORITY>;
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/* NRFX-6881: Temporary workaround for timer00 */
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max-frequency = <DT_FREQ_M(64)>;
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prescaler = <0>;
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};
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dppic10: dppic@82000 {
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compatible = "nordic,nrf-dppic";
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reg = <0x82000 0x808>;
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status = "disabled";
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};
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ppib10: ppib@83000 {
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compatible = "nordic,nrf-ppib";
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reg = <0x83000 0x1000>;
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status = "disabled";
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};
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ppib11: ppib@84000 {
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compatible = "nordic,nrf-ppib";
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reg = <0x84000 0x1000>;
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status = "disabled";
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};
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timer10: timer@85000 {
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compatible = "nordic,nrf-timer";
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status = "disabled";
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reg = <0x85000 0x1000>;
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cc-num = <8>;
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max-bit-width = <32>;
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interrupts = <133 NRF_DEFAULT_IRQ_PRIORITY>;
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max-frequency = <DT_FREQ_M(32)>;
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prescaler = <0>;
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};
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egu10: egu@87000 {
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compatible = "nordic,nrf-egu";
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reg = <0x87000 0x1000>;
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interrupts = <135 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "disabled";
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};
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radio: radio@8a000 {
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compatible = "nordic,nrf-radio";
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reg = <0x8a000 0x1000>;
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interrupts = <138 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "disabled";
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dfe-supported;
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ieee802154-supported;
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ble-2mbps-supported;
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ble-coded-phy-supported;
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cs-supported;
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ieee802154: ieee802154 {
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compatible = "nordic,nrf-ieee802154";
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status = "disabled";
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};
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/* Note: In the nRF Connect SDK the SoftDevice Controller
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* is added and set as the default Bluetooth Controller.
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*/
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bt_hci_controller: bt_hci_controller {
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compatible = "zephyr,bt-hci-ll-sw-split";
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status = "disabled";
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};
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};
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dppic20: dppic@c2000 {
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compatible = "nordic,nrf-dppic";
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reg = <0xc2000 0x808>;
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status = "disabled";
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};
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ppib20: ppib@c3000 {
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compatible = "nordic,nrf-ppib";
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reg = <0xc3000 0x1000>;
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status = "disabled";
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};
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ppib21: ppib@c4000 {
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compatible = "nordic,nrf-ppib";
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reg = <0xc4000 0x1000>;
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status = "disabled";
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};
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ppib22: ppib@c5000 {
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compatible = "nordic,nrf-ppib";
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reg = <0xc5000 0x1000>;
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status = "disabled";
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};
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i2c20: i2c@c6000 {
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compatible = "nordic,nrf-twim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc6000 0x1000>;
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interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
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easydma-maxcnt-bits = <16>;
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status = "disabled";
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zephyr,pm-device-runtime-auto;
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};
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spi20: spi@c6000 {
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/*
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* This spi node can be either SPIM or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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compatible = "nordic,nrf-spim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc6000 0x1000>;
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interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
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max-frequency = <DT_FREQ_M(8)>;
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easydma-maxcnt-bits = <16>;
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rx-delay-supported;
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rx-delay = <1>;
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status = "disabled";
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};
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uart20: uart@c6000 {
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compatible = "nordic,nrf-uarte";
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reg = <0xc6000 0x1000>;
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interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "disabled";
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endtx-stoptx-supported;
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frame-timeout-supported;
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};
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i2c21: i2c@c7000 {
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compatible = "nordic,nrf-twim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc7000 0x1000>;
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interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
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easydma-maxcnt-bits = <16>;
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status = "disabled";
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zephyr,pm-device-runtime-auto;
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};
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spi21: spi@c7000 {
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/*
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* This spi node can be either SPIM or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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compatible = "nordic,nrf-spim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xc7000 0x1000>;
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interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
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max-frequency = <DT_FREQ_M(8)>;
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easydma-maxcnt-bits = <16>;
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rx-delay-supported;
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rx-delay = <1>;
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status = "disabled";
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};
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uart21: uart@c7000 {
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compatible = "nordic,nrf-uarte";
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reg = <0xc7000 0x1000>;
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interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "disabled";
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endtx-stoptx-supported;
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frame-timeout-supported;
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};
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egu20: egu@c9000 {
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compatible = "nordic,nrf-egu";
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reg = <0xc9000 0x1000>;
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interrupts = <201 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "disabled";
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};
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timer20: timer@ca000 {
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compatible = "nordic,nrf-timer";
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status = "disabled";
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reg = <0xca000 0x1000>;
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cc-num = <6>;
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max-bit-width = <32>;
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interrupts = <202 NRF_DEFAULT_IRQ_PRIORITY>;
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prescaler = <0>;
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};
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timer21: timer@cb000 {
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compatible = "nordic,nrf-timer";
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status = "disabled";
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reg = <0xcb000 0x1000>;
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cc-num = <6>;
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max-bit-width = <32>;
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interrupts = <203 NRF_DEFAULT_IRQ_PRIORITY>;
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prescaler = <0>;
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};
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timer22: timer@cc000 {
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compatible = "nordic,nrf-timer";
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status = "disabled";
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reg = <0xcc000 0x1000>;
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cc-num = <6>;
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max-bit-width = <32>;
|
||||
interrupts = <204 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer23: timer@cd000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xcd000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <205 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer24: timer@ce000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xce000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <206 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
adc: adc@d5000 {
|
||||
compatible = "nordic,nrf-saadc";
|
||||
reg = <0xd5000 0x1000>;
|
||||
interrupts = <213 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
temp: temp@d7000 {
|
||||
compatible = "nordic,nrf-temp";
|
||||
reg = <0xd7000 0x1000>;
|
||||
interrupts = <215 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@d8200 {
|
||||
compatible = "nordic,nrf-gpio";
|
||||
gpio-controller;
|
||||
reg = <0xd8200 0x300>;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <16>;
|
||||
status = "disabled";
|
||||
port = <1>;
|
||||
gpiote-instance = <&gpiote20>;
|
||||
};
|
||||
|
||||
gpiote20: gpiote@da000 {
|
||||
compatible = "nordic,nrf-gpiote";
|
||||
reg = <0xda000 0x1000>;
|
||||
status = "disabled";
|
||||
instance = <20>;
|
||||
};
|
||||
|
||||
grtc: grtc@e2000 {
|
||||
compatible = "nordic,nrf-grtc";
|
||||
reg = <0xe2000 0x1000>;
|
||||
cc-num = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dppic30: dppic@102000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0x102000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib30: ppib@103000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x103000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c30: i2c@104000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi30: spi@104000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart30: uart@104000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
clock: clock@10e000 {
|
||||
compatible = "nordic,nrf-clock";
|
||||
reg = <0x10e000 0x1000>;
|
||||
interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
power: power@10e000 {
|
||||
compatible = "nordic,nrf-power";
|
||||
reg = <0x10e000 0x1000>;
|
||||
ranges = <0x0 0x10e000 0x1000>;
|
||||
interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpregret1: gpregret1@51c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "nordic,nrf-gpregret";
|
||||
reg = <0x51c 0x1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpregret2: gpregret2@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "nordic,nrf-gpregret";
|
||||
reg = <0x520 0x1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
comp: comparator@106000 {
|
||||
/*
|
||||
* Use compatible "nordic,nrf-comp" to configure as COMP
|
||||
* Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP
|
||||
*/
|
||||
compatible = "nordic,nrf-comp";
|
||||
reg = <0x106000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupts = <262 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
#ifdef USE_NON_SECURE_ADDRESS_MAP
|
||||
/* intentionally empty because WDT30 is hardware fixed to Secure */
|
||||
#else
|
||||
wdt30: watchdog@108000 {
|
||||
compatible = "nordic,nrf-wdt";
|
||||
reg = <0x108000 0x620>;
|
||||
interrupts = <264 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
#endif
|
||||
|
||||
wdt31: watchdog@109000 {
|
||||
compatible = "nordic,nrf-wdt";
|
||||
reg = <0x109000 0x620>;
|
||||
interrupts = <265 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@10a000 {
|
||||
compatible = "nordic,nrf-gpio";
|
||||
gpio-controller;
|
||||
reg = <0x10a000 0x300>;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <5>;
|
||||
status = "disabled";
|
||||
port = <0>;
|
||||
gpiote-instance = <&gpiote30>;
|
||||
};
|
||||
|
||||
gpiote30: gpiote@10c000 {
|
||||
compatible = "nordic,nrf-gpiote";
|
||||
reg = <0x10c000 0x1000>;
|
||||
status = "disabled";
|
||||
instance = <30>;
|
||||
};
|
||||
|
||||
regulators: regulator@120000 {
|
||||
compatible = "nordic,nrf54l-regulators";
|
||||
reg = <0x120000 0x1000>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
vregmain: regulator@120600 {
|
||||
compatible = "nordic,nrf5x-regulator";
|
||||
reg = <0x120600 0x1>;
|
||||
status = "disabled";
|
||||
regulator-name = "VREGMAIN";
|
||||
regulator-initial-mode = <NRF5X_REG_MODE_LDO>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rram_controller: rram-controller@5004e000 {
|
||||
compatible = "nordic,rram-controller";
|
||||
reg = <0x5004e000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <75 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
|
||||
/* 952 + 60 = 1012KB */
|
||||
cpuapp_rram: rram@0 {
|
||||
compatible = "soc-nv-flash";
|
||||
erase-block-size = <4096>;
|
||||
write-block-size = <16>;
|
||||
reg = <0x0 DT_SIZE_K(952)>;
|
||||
};
|
||||
|
||||
cpuflpr_rram: rram@ee000 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0xee000 DT_SIZE_K(60)>;
|
||||
erase-block-size = <4096>;
|
||||
write-block-size = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
cpuapp_ppb: cpuapp-ppb-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpuapp_nvic: interrupt-controller@e000e100 {
|
||||
#address-cells = <1>;
|
||||
compatible = "arm,v8m-nvic";
|
||||
reg = <0xe000e100 0xc00>;
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
cpuapp_systick: timer@e000e010 {
|
||||
compatible = "arm,armv8m-systick";
|
||||
reg = <0xe000e010 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -48,6 +48,8 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L05 NRF54L05_XXAA
|
|||
DEVELOP_IN_NRF54L15)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L05_CPUAPP NRF_APPLICATION)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L05_CPUFLPR NRF_FLPR)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L09_ENGA NRF54L09_ENGA_XXAA)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L09_ENGA_CPUAPP NRF_APPLICATION)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L10 NRF54L10_XXAA
|
||||
DEVELOP_IN_NRF54L15)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L10_CPUAPP NRF_APPLICATION)
|
||||
|
|
@ -190,9 +192,9 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG NRF_SKIP_C
|
|||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_DISABLE_FICR_TRIMCNF NRF_DISABLE_FICR_TRIMCNF)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE NRF_SKIP_GLITCHDETECTOR_DISABLE)
|
||||
|
||||
# Inject code to skip TAMPC setup for nRF54L20. It is not supported for now.
|
||||
# Inject code to skip TAMPC setup for nRF54L20 and nRF54L09. It is not supported for now.
|
||||
# It needs to be removed when support is provided.
|
||||
if(CONFIG_SOC_NRF54L20_ENGA_CPUAPP)
|
||||
if(CONFIG_SOC_NRF54L20_ENGA_CPUAPP OR CONFIG_SOC_NRF54L09_ENGA_CPUAPP)
|
||||
zephyr_compile_definitions(NRF_SKIP_TAMPC_SETUP)
|
||||
endif()
|
||||
|
||||
|
|
@ -230,6 +232,7 @@ mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUFLPR nrf54h20_flpr.svd)
|
|||
mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPURAD nrf54h20_radiocore.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L05_CPUAPP nrf54l05_application.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L05_CPUFLPR nrf54l05_flpr.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L09_ENGA_CPUAPP nrf54l09_enga_application.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L10_CPUAPP nrf54l10_application.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L10_CPUFLPR nrf54l10_flpr.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUAPP nrf54l15_application.svd)
|
||||
|
|
|
|||
|
|
@ -1136,6 +1136,8 @@
|
|||
#include <nrfx_config_nrf54l05_application.h>
|
||||
#elif defined(NRF54L05_XXAA) && defined(NRF_FLPR)
|
||||
#include <nrfx_config_nrf54l05_flpr.h>
|
||||
#elif defined(NRF54L09_ENGA_XXAA) && defined(NRF_APPLICATION)
|
||||
#include <nrfx_config_nrf54l09_enga_application.h>
|
||||
#elif defined(NRF54L10_XXAA) && defined(NRF_APPLICATION)
|
||||
#include <nrfx_config_nrf54l10_application.h>
|
||||
#elif defined(NRF54L10_XXAA) && defined(NRF_FLPR)
|
||||
|
|
|
|||
1355
modules/hal_nordic/nrfx/nrfx_config_nrf54l09_enga_application.h
Normal file
1355
modules/hal_nordic/nrfx/nrfx_config_nrf54l09_enga_application.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -25,6 +25,9 @@ config SOC_NRF54L_CPUAPP_COMMON
|
|||
config SOC_NRF54L05_CPUAPP
|
||||
select SOC_NRF54L_CPUAPP_COMMON
|
||||
|
||||
config SOC_NRF54L09_ENGA_CPUAPP
|
||||
select SOC_NRF54L_CPUAPP_COMMON
|
||||
|
||||
config SOC_NRF54L10_CPUAPP
|
||||
select SOC_NRF54L_CPUAPP_COMMON
|
||||
|
||||
|
|
|
|||
14
soc/nordic/nrf54l/Kconfig.defconfig.nrf54l09_enga_cpuapp
Normal file
14
soc/nordic/nrf54l/Kconfig.defconfig.nrf54l09_enga_cpuapp
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Nordic Semiconductor nRF54L09 MCU
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF54L09_ENGA_CPUAPP
|
||||
|
||||
config NUM_IRQS
|
||||
default 274
|
||||
|
||||
config IEEE802154_NRF5
|
||||
default IEEE802154
|
||||
|
||||
endif # SOC_NRF54L09_ENGA_CPUAPP
|
||||
|
|
@ -21,6 +21,24 @@ config SOC_NRF54L05_CPUFLPR
|
|||
help
|
||||
NRF54L05 CPUFLPR
|
||||
|
||||
config SOC_NRF54L09
|
||||
bool
|
||||
select SOC_SERIES_NRF54LX
|
||||
help
|
||||
NRF54L09
|
||||
|
||||
config SOC_NRF54L09_ENGA
|
||||
bool
|
||||
select SOC_NRF54L09
|
||||
help
|
||||
NRF54L09 ENGA
|
||||
|
||||
config SOC_NRF54L09_ENGA_CPUAPP
|
||||
bool
|
||||
select SOC_NRF54L09_ENGA
|
||||
help
|
||||
NRF54L09 ENGA CPUAPP
|
||||
|
||||
config SOC_NRF54L10
|
||||
bool
|
||||
select SOC_SERIES_NRF54LX
|
||||
|
|
@ -77,6 +95,7 @@ config SOC_NRF54L20_ENGA_CPUAPP
|
|||
|
||||
config SOC
|
||||
default "nrf54l05" if SOC_NRF54L05
|
||||
default "nrf54l09" if SOC_NRF54L09
|
||||
default "nrf54l10" if SOC_NRF54L10
|
||||
default "nrf54l15" if SOC_NRF54L15
|
||||
default "nrf54l20" if SOC_NRF54L20
|
||||
|
|
|
|||
|
|
@ -25,6 +25,9 @@ family:
|
|||
cpuclusters:
|
||||
- name: cpuapp
|
||||
- name: cpuflpr
|
||||
- name: nrf54l09
|
||||
cpuclusters:
|
||||
- name: cpuapp
|
||||
- name: nrf54l10
|
||||
cpuclusters:
|
||||
- name: cpuapp
|
||||
|
|
@ -105,6 +108,8 @@ runners:
|
|||
- qualifiers:
|
||||
- nrf54l05/cpuapp
|
||||
- nrf54l05/cpuflpr
|
||||
- qualifiers:
|
||||
- nrf54l09/cpuapp
|
||||
- qualifiers:
|
||||
- nrf54l10/cpuapp
|
||||
- nrf54l10/cpuflpr
|
||||
|
|
@ -165,6 +170,8 @@ runners:
|
|||
- qualifiers:
|
||||
- nrf54l05/cpuapp
|
||||
- nrf54l05/cpuflpr
|
||||
- qualifiers:
|
||||
- nrf54l09/cpuapp
|
||||
- qualifiers:
|
||||
- nrf54l10/cpuapp
|
||||
- nrf54l10/cpuflpr
|
||||
|
|
|
|||
Loading…
Reference in a new issue