adafruit-mirror/zephyr
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 8

counter: nxp_s32_sys_timer: use clock control APIs

Browse source 
Use clock control API to retrieve the counter module's frequency and
update the boards using it to provide the source clocks.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-09-15 16:25:28 +07:00 committed by Carles Cufí
parent 066cc2c9d2
commit b38dab48c6
6 changed files with 38 additions and 24 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi
View file

@ -6,22 +6,6 @@
#include "s32z270dc2_r52-pinctrl-common.dtsi"
&stm0 {
clock-frequency = <133333333>;
};
&stm1 {
clock-frequency = <133333333>;
};
&stm2 {
clock-frequency = <133333333>;
};
&stm3 {
clock-frequency = <133333333>;
};
&swt0 {
status = "okay";
};

3
drivers/counter/Kconfig.nxp_s32
View file

@ -1,9 +1,10 @@
# Copyright 2022 NXP
# Copyright 2022-2023 NXP
# SPDX-License-Identifier: Apache-2.0
config COUNTER_NXP_S32_SYS_TIMER
bool "NXP S32 System Timer Module driver"
default y
depends on DT_HAS_NXP_S32_SYS_TIMER_ENABLED
select CLOCK_CONTROL
help
Enable support for NXP S32 System Timer Module (STM) driver.

29
drivers/counter/counter_nxp_s32_sys_timer.c
View file

@ -1,10 +1,11 @@
/*
* Copyright 2022 NXP
* Copyright 2022-2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/counter.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <soc.h>
@ -35,6 +36,8 @@ struct nxp_s32_sys_timer_config {
Stm_Ip_InstanceConfigType hw_cfg;
Stm_Ip_ChannelConfigType ch_cfg[SYS_TIMER_NUM_CHANNELS];
uint8_t instance;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
};
static int nxp_s32_sys_timer_start(const struct device *dev)
@ -145,8 +148,14 @@ static uint32_t nxp_s32_sys_timer_get_top_value(const struct device *dev)
static uint32_t nxp_s32_sys_timer_get_frequency(const struct device *dev)
{
const struct nxp_s32_sys_timer_config *config = dev->config;
uint32_t clock_rate;
return config->info.freq / (config->hw_cfg.clockPrescaler + 1U);
if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate)) {
LOG_ERR("Failed to get clock frequency");
return 0;
}
return clock_rate / (config->hw_cfg.clockPrescaler + 1U);
}
static int nxp_s32_sys_timer_init(const struct device *dev)
@ -155,6 +164,18 @@ static int nxp_s32_sys_timer_init(const struct device *dev)
struct nxp_s32_sys_timer_data *data = dev->data;
struct nxp_s32_sys_timer_chan_data *ch_data;
int i;
int err;
if (!device_is_ready(config->clock_dev)) {
LOG_ERR("Clock control device not ready");
return -ENODEV;
}
err = clock_control_on(config->clock_dev, config->clock_subsys);
if (err) {
LOG_ERR("Failed to enable clock");
return err;
}
Stm_Ip_Init(config->instance, &config->hw_cfg);
@ -227,7 +248,6 @@ static const struct counter_driver_api nxp_s32_sys_timer_driver_api = {
static const struct nxp_s32_sys_timer_config nxp_s32_sys_timer_config_##n = { \
.info = { \
.max_top_value = SYS_TIMER_MAX_VALUE, \
.freq = (DT_PROP(SYS_TIMER_NODE(n), clock_frequency)), \
.channels = SYS_TIMER_NUM_CHANNELS, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
}, \
@ -239,6 +259,9 @@ static const struct counter_driver_api nxp_s32_sys_timer_driver_api = {
LISTIFY(SYS_TIMER_NUM_CHANNELS, SYS_TIMER_CHANNEL_CFG, (,), n) \
}, \
.instance = SYS_TIMER_INSTANCE_ID(n), \
.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(SYS_TIMER_NODE(n))), \
.clock_subsys = (clock_control_subsys_t) \
DT_CLOCKS_CELL(SYS_TIMER_NODE(n), name), \
}; \
\
DEVICE_DT_DEFINE(SYS_TIMER_NODE(n), \

4
dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi
View file

@ -20,6 +20,7 @@
compatible = "nxp,s32-sys-timer";
reg = <0x76200000 0x10000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
status = "disabled";
};
@ -27,6 +28,7 @@
compatible = "nxp,s32-sys-timer";
reg = <0x76210000 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
status = "disabled";
};
@ -34,6 +36,7 @@
compatible = "nxp,s32-sys-timer";
reg = <0x76020000 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
status = "disabled";
};
@ -41,6 +44,7 @@
compatible = "nxp,s32-sys-timer";
reg = <0x76030000 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
status = "disabled";
};

4
dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi
View file

@ -20,6 +20,7 @@
compatible = "nxp,s32-sys-timer";
reg = <0x76a00000 0x10000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
status = "disabled";
};
@ -27,6 +28,7 @@
compatible = "nxp,s32-sys-timer";
reg = <0x76a10000 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
status = "disabled";
};
@ -34,6 +36,7 @@
compatible = "nxp,s32-sys-timer";
reg = <0x76820000 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
status = "disabled";
};
@ -41,6 +44,7 @@
compatible = "nxp,s32-sys-timer";
reg = <0x76830000 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
status = "disabled";
};

6
dts/bindings/timer/nxp,s32-sys-timer.yaml
View file

@ -1,4 +1,4 @@
# Copyright 2022 NXP
# Copyright 2022-2023 NXP
# SPDX-License-Identifier: Apache-2.0
description: NXP S32 System Timer Module (STM)
@ -14,10 +14,8 @@ properties:
interrupts:
required: true
clock-frequency:
type: int
clocks:
required: true
description: Module clock frequency in Hz.
prescaler:
type: int