diff --git a/arch/xtensa/core/coredump.c b/arch/xtensa/core/coredump.c index 8f15ca39c58..26060dea8c3 100644 --- a/arch/xtensa/core/coredump.c +++ b/arch/xtensa/core/coredump.c @@ -19,6 +19,7 @@ enum xtensa_soc_code { XTENSA_SOC_INTEL_ADSP, XTENSA_SOC_ESP32S2, XTENSA_SOC_ESP32S3, + XTENSA_SOC_DC233C, }; struct xtensa_arch_block { @@ -117,6 +118,8 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf) arch_blk.soc = XTENSA_SOC_ESP32S2; #elif CONFIG_SOC_SERIES_ESP32S3 arch_blk.soc = XTENSA_SOC_ESP32S3; + #elif CONFIG_SOC_XTENSA_DC233C + arch_blk.soc = XTENSA_SOC_DC233C; #else arch_blk.soc = XTENSA_SOC_UNKNOWN; #endif diff --git a/scripts/coredump/gdbstubs/arch/xtensa.py b/scripts/coredump/gdbstubs/arch/xtensa.py index dfc2f48453e..fbe572ac16b 100644 --- a/scripts/coredump/gdbstubs/arch/xtensa.py +++ b/scripts/coredump/gdbstubs/arch/xtensa.py @@ -25,6 +25,7 @@ class XtensaSoc(Enum): INTEL_ADSP_CAVS = 3 ESP32S2 = 4 ESP32S3 = 5 + DC233C = 6 # The previous version of this script didn't need to know @@ -68,6 +69,8 @@ def get_gdb_reg_definition(soc, toolchain): return GdbRegDef_ESP32S2 elif soc == XtensaSoc.ESP32S3: return GdbRegDef_ESP32S3 + elif soc == XtensaSoc.DC233C: + return GdbRegDef_DC233C else: raise NotImplementedError @@ -476,3 +479,38 @@ class GdbRegDef_Intel_Adsp_CAVS_XCC: LCOUNT = 514 WINDOWBASE = 584 WINDOWSTART = 585 + +# sdk-ng -> overlays/xtensa_dc233c/gdb/gdb/xtensa-config.c +class GdbRegDef_DC233C: + ARCH_DATA_BLK_STRUCT_REGS = '