arch: riscv: add ARCH_HAS_SINGLE_THREAD_SUPPORT

Enable single-threading support for the riscv architecture.

Add z_riscv_switch_to_main_no_multithreading function for
supporting single-threading.

The single-threading does not work with enabling PMP_STACK_GUARD.
It is because single-threading does not use context-switching.
But the privileged mode transition that PMP depends on implicitly
presupposes using context-switching. It is a contradiction.
Thus, disable PMP_STACK_GUARD when MULTITHREADING is not enabled.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>

arch/riscv/Kconfig

@@ -242,6 +242,7 @@ endif #RISCV_PMP
 
 config PMP_STACK_GUARD
 	def_bool y
+	depends on MULTITHREADING
 	depends on HW_STACK_PROTECTION
 
 config PMP_STACK_GUARD_MIN_SIZE
@@ -280,6 +281,9 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN
 config GEN_IRQ_VECTOR_TABLE
 	select RISCV_MTVEC_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGE
 
+config ARCH_HAS_SINGLE_THREAD_SUPPORT
+	default y if !SMP
+
 rsource "Kconfig.isa"
 rsource "Kconfig.core"
 

arch/riscv/core/isr.S

@@ -557,6 +557,7 @@ irq_done:
 
 check_reschedule:
 
+#ifdef CONFIG_MULTITHREADING
 	/* Get pointer to current thread on this CPU */
 	lr a1, ___cpu_t_current_OFFSET(s0)
 
@@ -572,6 +573,9 @@ check_reschedule:
 	lr a1, 0(sp)
 	addi sp, sp, 16
 	beqz a0, no_reschedule
+#else
+	j no_reschedule
+#endif /* CONFIG_MULTITHREADING */
 
 reschedule:
 

arch/riscv/core/smp.c

@@ -46,7 +46,7 @@ void z_riscv_secondary_cpu_init(int hartid)
 #ifdef CONFIG_SMP
 	_kernel.cpus[cpu_num].arch.online = true;
 #endif
-#ifdef CONFIG_THREAD_LOCAL_STORAGE
+#if defined(CONFIG_MULTITHREADING) && defined(CONFIG_THREAD_LOCAL_STORAGE)
 	__asm__("mv tp, %0" : : "r" (z_idle_threads[cpu_num].tls));
 #endif
 #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)

arch/riscv/core/thread.c

@@ -190,3 +190,39 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
 }
 
 #endif /* CONFIG_USERSPACE */
+
+#ifndef CONFIG_MULTITHREADING
+
+K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_ISR_STACK_SIZE);
+K_THREAD_STACK_DECLARE(z_main_stack, CONFIG_MAIN_STACK_SIZE);
+
+FUNC_NORETURN void z_riscv_switch_to_main_no_multithreading(k_thread_entry_t main_entry,
+							    void *p1, void *p2, void *p3)
+{
+	void *main_stack;
+
+	ARG_UNUSED(p1);
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	_kernel.cpus[0].id = 0;
+	_kernel.cpus[0].irq_stack = (Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]) +
+				     K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]));
+
+	main_stack = (Z_THREAD_STACK_BUFFER(z_main_stack) +
+		      K_THREAD_STACK_SIZEOF(z_main_stack));
+
+	__asm__ volatile (
+	"mv sp, %0; jalr ra, %1, 0"
+	:
+	: "r" (main_stack), "r" (main_entry)
+	: "memory");
+
+	/* infinite loop */
+	irq_lock();
+	while (true) {
+	}
+
+	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
+}
+#endif /* !CONFIG_MULTITHREADING */

arch/riscv/include/kernel_arch_func.h

@@ -99,6 +99,15 @@ void z_riscv_flush_local_fpu(void);
 void z_riscv_flush_fpu_ipi(unsigned int cpu);
 #endif
 
+#ifndef CONFIG_MULTITHREADING
+extern FUNC_NORETURN void z_riscv_switch_to_main_no_multithreading(
+	k_thread_entry_t main_func, void *p1, void *p2, void *p3);
+
+#define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING \
+	z_riscv_switch_to_main_no_multithreading
+
+#endif /* !CONFIG_MULTITHREADING */
+
 #endif /* _ASMLANGUAGE */
 
 #ifdef __cplusplus