diff --git a/drivers/dma/Kconfig.stm32 b/drivers/dma/Kconfig.stm32 index 0e35afd0367..44b2971ce50 100644 --- a/drivers/dma/Kconfig.stm32 +++ b/drivers/dma/Kconfig.stm32 @@ -54,7 +54,8 @@ config DMAMUX_STM32 config DMA_STM32_SHARED_IRQS bool default y - depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32G0X || SOC_SERIES_STM32L0X + depends on SOC_SERIES_STM32C0X || SOC_SERIES_STM32F0X || \ + SOC_SERIES_STM32G0X || SOC_SERIES_STM32L0X help Enable shared IRQ support on devices where channels share 1 IRQ. diff --git a/drivers/dma/dma_stm32.c b/drivers/dma/dma_stm32.c index b9cde124d8d..24d3c3f97e0 100644 --- a/drivers/dma/dma_stm32.c +++ b/drivers/dma/dma_stm32.c @@ -36,8 +36,10 @@ LOG_MODULE_REGISTER(dma_stm32, CONFIG_DMA_LOG_LEVEL); #define DMA_STM32_0_STREAM_COUNT 7 #elif DT_INST_IRQ_HAS_IDX(0, 5) #define DMA_STM32_0_STREAM_COUNT 6 -#else +#elif DT_INST_IRQ_HAS_IDX(0, 4) #define DMA_STM32_0_STREAM_COUNT 5 +#else +#define DMA_STM32_0_STREAM_COUNT 3 #endif #endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */ @@ -765,6 +767,7 @@ static void dma_stm32_irq_##dma##_##chan(const struct device *dev) \ DMA_STM32_DEFINE_IRQ_HANDLER(0, 0); DMA_STM32_DEFINE_IRQ_HANDLER(0, 1); DMA_STM32_DEFINE_IRQ_HANDLER(0, 2); +#if DT_INST_IRQ_HAS_IDX(0, 3) DMA_STM32_DEFINE_IRQ_HANDLER(0, 3); DMA_STM32_DEFINE_IRQ_HANDLER(0, 4); #if DT_INST_IRQ_HAS_IDX(0, 5) @@ -773,6 +776,7 @@ DMA_STM32_DEFINE_IRQ_HANDLER(0, 5); DMA_STM32_DEFINE_IRQ_HANDLER(0, 6); #if DT_INST_IRQ_HAS_IDX(0, 7) DMA_STM32_DEFINE_IRQ_HANDLER(0, 7); +#endif /* DT_INST_IRQ_HAS_IDX(0, 3) */ #endif /* DT_INST_IRQ_HAS_IDX(0, 5) */ #endif /* DT_INST_IRQ_HAS_IDX(0, 6) */ #endif /* DT_INST_IRQ_HAS_IDX(0, 7) */ @@ -786,6 +790,7 @@ static void dma_stm32_config_irq_0(const struct device *dev) #ifndef CONFIG_DMA_STM32_SHARED_IRQS DMA_STM32_IRQ_CONNECT(0, 2); #endif /* CONFIG_DMA_STM32_SHARED_IRQS */ +#if DT_INST_IRQ_HAS_IDX(0, 3) DMA_STM32_IRQ_CONNECT(0, 3); #ifndef CONFIG_DMA_STM32_SHARED_IRQS DMA_STM32_IRQ_CONNECT(0, 4); @@ -795,11 +800,12 @@ static void dma_stm32_config_irq_0(const struct device *dev) DMA_STM32_IRQ_CONNECT(0, 6); #if DT_INST_IRQ_HAS_IDX(0, 7) DMA_STM32_IRQ_CONNECT(0, 7); +#endif /* DT_INST_IRQ_HAS_IDX(0, 3) */ #endif /* DT_INST_IRQ_HAS_IDX(0, 5) */ #endif /* DT_INST_IRQ_HAS_IDX(0, 6) */ #endif /* DT_INST_IRQ_HAS_IDX(0, 7) */ #endif /* CONFIG_DMA_STM32_SHARED_IRQS */ -/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */ +/* Either 3 or 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */ } DMA_STM32_INIT_DEV(0); diff --git a/drivers/dma/dma_stm32_v2.c b/drivers/dma/dma_stm32_v2.c index 44781fe46c6..d7cebe50a7e 100644 --- a/drivers/dma/dma_stm32_v2.c +++ b/drivers/dma/dma_stm32_v2.c @@ -21,6 +21,7 @@ uint32_t dma_stm32_id_to_stream(uint32_t id) LL_DMA_CHANNEL_1, LL_DMA_CHANNEL_2, LL_DMA_CHANNEL_3, +#if defined(LL_DMA_CHANNEL_4) LL_DMA_CHANNEL_4, LL_DMA_CHANNEL_5, #if defined(LL_DMA_CHANNEL_6) @@ -32,6 +33,7 @@ uint32_t dma_stm32_id_to_stream(uint32_t id) #endif /* LL_DMA_CHANNEL_8 */ #endif /* LL_DMA_CHANNEL_7 */ #endif /* LL_DMA_CHANNEL_6 */ +#endif /* LL_DMA_CHANNEL_4 */ }; __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); @@ -45,6 +47,7 @@ void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_ClearFlag_HT1, LL_DMA_ClearFlag_HT2, LL_DMA_ClearFlag_HT3, +#if defined(LL_DMA_IFCR_CHTIF4) LL_DMA_ClearFlag_HT4, LL_DMA_ClearFlag_HT5, #if defined(LL_DMA_IFCR_CHTIF6) @@ -56,6 +59,7 @@ void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id) #endif /* LL_DMA_IFCR_CHTIF8 */ #endif /* LL_DMA_IFCR_CHTIF7 */ #endif /* LL_DMA_IFCR_CHTIF6 */ +#endif /* LL_DMA_IFCR_CHTIF4 */ }; __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); @@ -69,6 +73,7 @@ void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_TC3, +#if defined(LL_DMA_IFCR_CTCIF4) LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_TC5, #if defined(LL_DMA_IFCR_CTCIF6) @@ -80,6 +85,7 @@ void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id) #endif /* LL_DMA_IFCR_CTCIF8 */ #endif /* LL_DMA_IFCR_CTCIF7 */ #endif /* LL_DMA_IFCR_CTCIF6 */ +#endif /* LL_DMA_IFCR_CTCIF4 */ }; __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); @@ -93,6 +99,7 @@ bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_IsActiveFlag_HT1, LL_DMA_IsActiveFlag_HT2, LL_DMA_IsActiveFlag_HT3, +#if defined(LL_DMA_IFCR_CHTIF4) LL_DMA_IsActiveFlag_HT4, LL_DMA_IsActiveFlag_HT5, #if defined(LL_DMA_IFCR_CHTIF6) @@ -104,6 +111,7 @@ bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id) #endif /* LL_DMA_IFCR_CHTIF8 */ #endif /* LL_DMA_IFCR_CHTIF7 */ #endif /* LL_DMA_IFCR_CHTIF6 */ +#endif /* LL_DMA_IFCR_CHTIF4 */ }; __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); @@ -117,6 +125,7 @@ bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_IsActiveFlag_TC1, LL_DMA_IsActiveFlag_TC2, LL_DMA_IsActiveFlag_TC3, +#if defined(LL_DMA_IFCR_CTCIF4) LL_DMA_IsActiveFlag_TC4, LL_DMA_IsActiveFlag_TC5, #if defined(LL_DMA_IFCR_CTCIF6) @@ -128,6 +137,7 @@ bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id) #endif /* LL_DMA_IFCR_CTCIF8 */ #endif /* LL_DMA_IFCR_CTCIF7 */ #endif /* LL_DMA_IFCR_CTCIF6 */ +#endif /* LL_DMA_IFCR_CTCIF4 */ }; __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); @@ -142,6 +152,7 @@ void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_ClearFlag_TE1, LL_DMA_ClearFlag_TE2, LL_DMA_ClearFlag_TE3, +#if defined(LL_DMA_IFCR_CTEIF4) LL_DMA_ClearFlag_TE4, LL_DMA_ClearFlag_TE5, #if defined(LL_DMA_IFCR_CTEIF6) @@ -150,6 +161,7 @@ void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_ClearFlag_TE7, #if defined(LL_DMA_IFCR_CTEIF8) LL_DMA_ClearFlag_TE8, +#endif /* LL_DMA_IFCR_CTEIF4 */ #endif /* LL_DMA_IFCR_CTEIF6 */ #endif /* LL_DMA_IFCR_CTEIF7 */ #endif /* LL_DMA_IFCR_CTEIF8 */ @@ -166,6 +178,7 @@ void dma_stm32_clear_gi(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_ClearFlag_GI1, LL_DMA_ClearFlag_GI2, LL_DMA_ClearFlag_GI3, +#if defined(LL_DMA_IFCR_CGIF4) LL_DMA_ClearFlag_GI4, LL_DMA_ClearFlag_GI5, #if defined(LL_DMA_IFCR_CGIF6) @@ -174,6 +187,7 @@ void dma_stm32_clear_gi(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_ClearFlag_GI7, #if defined(LL_DMA_IFCR_CGIF8) LL_DMA_ClearFlag_GI8, +#endif /* LL_DMA_IFCR_CGIF4 */ #endif /* LL_DMA_IFCR_CGIF6 */ #endif /* LL_DMA_IFCR_CGIF7 */ #endif /* LL_DMA_IFCR_CGIF8 */ @@ -190,6 +204,7 @@ bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_IsActiveFlag_TE1, LL_DMA_IsActiveFlag_TE2, LL_DMA_IsActiveFlag_TE3, +#if defined(LL_DMA_IFCR_CTEIF4) LL_DMA_IsActiveFlag_TE4, LL_DMA_IsActiveFlag_TE5, #if defined(LL_DMA_IFCR_CTEIF6) @@ -198,6 +213,7 @@ bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_IsActiveFlag_TE7, #if defined(LL_DMA_IFCR_CTEIF8) LL_DMA_IsActiveFlag_TE8, +#endif /* LL_DMA_IFCR_CTEIF4 */ #endif /* LL_DMA_IFCR_CTEIF6 */ #endif /* LL_DMA_IFCR_CTEIF7 */ #endif /* LL_DMA_IFCR_CTEIF8 */ @@ -214,6 +230,7 @@ bool dma_stm32_is_gi_active(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_IsActiveFlag_GI1, LL_DMA_IsActiveFlag_GI2, LL_DMA_IsActiveFlag_GI3, +#if defined(LL_DMA_IFCR_CGIF4) LL_DMA_IsActiveFlag_GI4, LL_DMA_IsActiveFlag_GI5, #if defined(LL_DMA_IFCR_CGIF6) @@ -222,6 +239,7 @@ bool dma_stm32_is_gi_active(DMA_TypeDef *DMAx, uint32_t id) LL_DMA_IsActiveFlag_GI7, #if defined(LL_DMA_IFCR_CGIF8) LL_DMA_IsActiveFlag_GI8, +#endif /* LL_DMA_IFCR_CGIF4 */ #endif /* LL_DMA_IFCR_CGIF6 */ #endif /* LL_DMA_IFCR_CGIF7 */ #endif /* LL_DMA_IFCR_CGIF8 */