drivers: gpio: implement driver for TLE9104
Implement a driver for the powertrain switch TLE9104. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This commit is contained in:
Benedikt Schmidt
Fabio Baltieri
parent
4d554dd30c
commit
bfb8eda025
4 changed files with 557 additions and 0 deletions
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@ -84,6 +84,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_NUMAKER gpio_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_EFINIX_SAPPHIRE gpio_efinix_sapphire.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_DAVINCI gpio_davinci.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_SEDI gpio_sedi.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TLE9104 gpio_tle9104.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ALTERA_PIO gpio_altera_pio.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BCM2711 gpio_bcm2711.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RA gpio_ra.c)
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@ -226,6 +226,8 @@ source "drivers/gpio/Kconfig.efinix_sapphire"
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source "drivers/gpio/Kconfig.davinci"
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source "drivers/gpio/Kconfig.sedi"
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source "drivers/gpio/Kconfig.tle9104"
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source "drivers/gpio/Kconfig.altera"
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source "drivers/gpio/Kconfig.bcm2711"
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19
drivers/gpio/Kconfig.tle9104
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19
drivers/gpio/Kconfig.tle9104
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@ -0,0 +1,19 @@
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# TLE9104 GPIO configuration options
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# Copyright (c) 2023 SILA Embedded Solutions GmbH
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# SPDX-License-Identifier: Apache-2.0
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menuconfig GPIO_TLE9104
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bool "TLE9104 SPI-based powertrain switch"
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default y
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depends on DT_HAS_INFINEON_TLE9104_ENABLED
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depends on SPI
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help
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Enable driver for TLE9104 SPI-based powertrain switch.
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config GPIO_TLE9104_INIT_PRIORITY
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int "Init priority"
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default 75
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depends on GPIO_TLE9104
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help
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Device driver initialization priority.
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535
drivers/gpio/gpio_tle9104.c
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535
drivers/gpio/gpio_tle9104.c
Normal file
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@ -0,0 +1,535 @@
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/*
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* Copyright (c) 2023 SILA Embedded Solutions GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT infineon_tle9104
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/byteorder.h>
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LOG_MODULE_REGISTER(gpio_tle9104, CONFIG_GPIO_LOG_LEVEL);
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/*
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* The values for the defines below as well as the register definitions were
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* taken from the datasheet, which can be found at:
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* https://www.infineon.com/dgdl/Infineon-TLE9104SH-DataSheet-v01_31-EN.pdf?fileId=5546d462766cbe86017676144d76581b
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*/
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#define TLE9104_RESET_DURATION_TIME_US 10
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#define TLE9104_RESET_DURATION_WAIT_TIME_SAFETY_MARGIN_US 200
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#define TLE9104_RESET_DURATION_WAIT_TIME_US 10
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#define TLE9104_GPIO_COUNT 4
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#define TLE9104_INITIALIZATION_TIMEOUT_MS 1
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#define TLE9104_ICVERSIONID 0xB1
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#define TLE9104_FRAME_RW_POS 15
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#define TLE9104_FRAME_PARITY_POS 14
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#define TLE9104_FRAME_FAULTCOMMUNICATION_POS 13
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#define TLE9104_FRAME_FAULTGLOBAL_POS 12
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#define TLE9104_FRAME_ADDRESS_POS 8
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#define TLE9104_FRAME_DATA_POS 0
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#define TLE9104_CFG_CWDTIME_LENGTH 2
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#define TLE9104_CFG_CWDTIME_POS 6
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#define TLE9104_CTRL_OUT1ONS_BIT BIT(1)
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#define TLE9104_CTRL_OUT1ONC_BIT BIT(0)
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#define TLE9104_CFG_OUT1DD_BIT BIT(0)
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#define TLE9104_GLOBALSTATUS_OUTEN_BIT BIT(7)
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#define TLE9104_GLOBALSTATUS_POR_LATCH_BIT BIT(0)
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#define TLE9104_SPIFRAME_FAULTCOMMUNICATION_BIT BIT(13)
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enum tle9104_register {
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TLE9104REGISTER_CTRL = 0x00,
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TLE9104REGISTER_CFG = 0x01,
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TLE9104REGISTER_GLOBALSTATUS = 0x07,
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TLE9104REGISTER_ICVID = 0x08,
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};
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struct tle9104_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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struct spi_dt_spec bus;
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const struct gpio_dt_spec gpio_reset;
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const struct gpio_dt_spec gpio_enable;
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const struct gpio_dt_spec gpio_control[TLE9104_GPIO_COUNT];
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};
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struct tle9104_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* each bit is one output channel, bit 0 = OUT1, ... */
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uint8_t state;
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/* same as state, just kept for checking what has to be updated */
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uint8_t previous_state;
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/* each bit defines if the output channel is configured, see state */
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uint8_t configured;
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struct k_mutex lock;
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};
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static void tle9104_set_cfg_cwdtime(uint8_t *destination, uint8_t value)
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{
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uint8_t length = TLE9104_CFG_CWDTIME_LENGTH;
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uint8_t pos = TLE9104_CFG_CWDTIME_POS;
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*destination &= ~GENMASK(pos + length - 1, pos);
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*destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value);
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}
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static int tle9104_calculate_parity(uint16_t value)
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{
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int parity = 1 + POPCOUNT(value);
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if ((value & BIT(TLE9104_FRAME_PARITY_POS)) != 0) {
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parity--;
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}
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return parity % 2;
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}
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static void tle9104_apply_parity(uint16_t *value)
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{
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int parity = tle9104_calculate_parity(*value);
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WRITE_BIT(*value, TLE9104_FRAME_PARITY_POS, parity);
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}
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static bool tle9104_check_parity(uint16_t value)
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{
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int parity = tle9104_calculate_parity(value);
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return ((value & BIT(TLE9104_FRAME_PARITY_POS)) >> TLE9104_FRAME_PARITY_POS) == parity;
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}
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static int tle9104_transceive_frame(const struct device *dev, bool write,
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enum tle9104_register write_reg, uint8_t write_data,
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enum tle9104_register *read_reg, uint8_t *read_data)
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{
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const struct tle9104_config *config = dev->config;
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uint16_t write_frame;
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uint16_t read_frame;
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int result;
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uint8_t buffer_tx[2];
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uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
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const struct spi_buf tx_buf[] = {{
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.buf = buffer_tx,
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.len = ARRAY_SIZE(buffer_tx),
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}};
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const struct spi_buf rx_buf[] = {{
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.buf = buffer_rx,
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.len = ARRAY_SIZE(buffer_rx),
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}};
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const struct spi_buf_set tx = {
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.buffers = tx_buf,
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.count = ARRAY_SIZE(tx_buf),
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};
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const struct spi_buf_set rx = {
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.buffers = rx_buf,
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.count = ARRAY_SIZE(rx_buf),
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};
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write_frame = write_data << TLE9104_FRAME_DATA_POS;
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write_frame |= write_reg << TLE9104_FRAME_ADDRESS_POS;
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WRITE_BIT(write_frame, TLE9104_FRAME_RW_POS, write);
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tle9104_apply_parity(&write_frame);
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sys_put_be16(write_frame, buffer_tx);
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LOG_DBG("writing in register 0x%02X of TLE9104 value 0x%02X, complete frame 0x%04X",
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write_reg, write_data, write_frame);
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result = spi_transceive_dt(&config->bus, &tx, &rx);
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if (result != 0) {
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LOG_ERR("spi_write failed with error %i", result);
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return result;
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}
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read_frame = sys_get_be16(buffer_rx);
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LOG_DBG("received complete frame 0x%04X", read_frame);
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if (!tle9104_check_parity(read_frame)) {
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LOG_ERR("parity check for received frame of TLE9104 failed");
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return -EIO;
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}
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if ((TLE9104_SPIFRAME_FAULTCOMMUNICATION_BIT & read_frame) != 0) {
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LOG_WRN("communication fault reported by TLE9104");
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}
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*read_reg = FIELD_GET(GENMASK(TLE9104_FRAME_FAULTGLOBAL_POS - 1, TLE9104_FRAME_ADDRESS_POS),
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read_frame);
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*read_data = FIELD_GET(GENMASK(TLE9104_FRAME_ADDRESS_POS - 1, TLE9104_FRAME_DATA_POS),
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read_frame);
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return 0;
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}
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static int tle9104_write_register(const struct device *dev, enum tle9104_register reg,
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uint8_t value)
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{
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enum tle9104_register read_reg;
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uint8_t read_data;
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return tle9104_transceive_frame(dev, true, reg, value, &read_reg, &read_data);
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}
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static int tle9104_write_state(const struct device *dev)
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{
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const struct tle9104_config *config = dev->config;
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struct tle9104_data *data = dev->data;
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bool spi_update_required = false;
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uint8_t register_ctrl = 0x00;
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int result;
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LOG_DBG("writing state 0x%02X to TLE9104", data->state);
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for (size_t i = 0; i < TLE9104_GPIO_COUNT; ++i) {
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uint8_t mask = GENMASK(i, i);
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bool current_value = (data->state & mask) != 0;
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bool previous_value = (data->previous_state & mask) != 0;
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/*
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* Setting the OUTx_ON bits results in a high impedance output,
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* clearing them pulls the output to ground. Therefore the
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* meaning here is intentionally inverted, as this will then turn
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* out for a low active open drain output to be pulled to ground
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* if set to off.
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*/
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if (current_value == 0) {
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register_ctrl |= TLE9104_CTRL_OUT1ONS_BIT << (2 * i);
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} else {
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register_ctrl |= TLE9104_CTRL_OUT1ONC_BIT << (2 * i);
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}
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if (current_value == previous_value) {
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continue;
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}
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if (config->gpio_control[i].port == NULL) {
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spi_update_required = true;
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continue;
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}
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result = gpio_pin_set_dt(&config->gpio_control[i], current_value);
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if (result != 0) {
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LOG_ERR("unable to set control GPIO");
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return result;
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}
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}
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if (spi_update_required) {
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result = tle9104_write_register(dev, TLE9104REGISTER_CTRL, register_ctrl);
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if (result != 0) {
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LOG_ERR("unable to set control register");
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return result;
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}
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}
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data->previous_state = data->state;
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return 0;
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}
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static int tle9104_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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struct tle9104_data *data = dev->data;
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int result;
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/* cannot execute a bus operation in an ISR context */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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if (pin >= TLE9104_GPIO_COUNT) {
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LOG_ERR("invalid pin nummber %i", pin);
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return -EINVAL;
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}
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if ((flags & GPIO_INPUT) != 0) {
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LOG_ERR("cannot configure pin as input");
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return -ENOTSUP;
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}
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if ((flags & GPIO_OUTPUT) == 0) {
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LOG_ERR("pin must be configured as an output");
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) == 0) {
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LOG_ERR("pin must be configured as single ended");
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return -ENOTSUP;
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}
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if ((flags & GPIO_LINE_OPEN_DRAIN) == 0) {
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LOG_ERR("pin must be configured as open drain");
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return -ENOTSUP;
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}
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if ((flags & GPIO_PULL_UP) != 0) {
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LOG_ERR("pin cannot have a pull up configured");
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return -ENOTSUP;
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}
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if ((flags & GPIO_PULL_DOWN) != 0) {
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LOG_ERR("pin cannot have a pull down configured");
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return -ENOTSUP;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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WRITE_BIT(data->state, pin, 0);
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} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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WRITE_BIT(data->state, pin, 1);
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}
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WRITE_BIT(data->configured, pin, 1);
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result = tle9104_write_state(dev);
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k_mutex_unlock(&data->lock);
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return result;
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}
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static int tle9104_port_get_raw(const struct device *dev, uint32_t *value)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(value);
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LOG_ERR("input pins are not available");
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return -ENOTSUP;
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}
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static int tle9104_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
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{
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struct tle9104_data *data = dev->data;
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int result;
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/* cannot execute a bus operation in an ISR context */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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data->state = (data->state & ~mask) | (mask & value);
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result = tle9104_write_state(dev);
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k_mutex_unlock(&data->lock);
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return result;
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}
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static int tle9104_port_set_bits_raw(const struct device *dev, uint32_t mask)
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{
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return tle9104_port_set_masked_raw(dev, mask, mask);
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}
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static int tle9104_port_clear_bits_raw(const struct device *dev, uint32_t mask)
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{
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return tle9104_port_set_masked_raw(dev, mask, 0);
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}
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static int tle9104_port_toggle_bits(const struct device *dev, uint32_t mask)
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{
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struct tle9104_data *data = dev->data;
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int result;
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/* cannot execute a bus operation in an ISR context */
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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data->state ^= mask;
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result = tle9104_write_state(dev);
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k_mutex_unlock(&data->lock);
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return result;
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}
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static int tle9104_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(pin);
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ARG_UNUSED(mode);
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ARG_UNUSED(trig);
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return -ENOTSUP;
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}
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static const struct gpio_driver_api api_table = {
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.pin_configure = tle9104_pin_configure,
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.port_get_raw = tle9104_port_get_raw,
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.port_set_masked_raw = tle9104_port_set_masked_raw,
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.port_set_bits_raw = tle9104_port_set_bits_raw,
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.port_clear_bits_raw = tle9104_port_clear_bits_raw,
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.port_toggle_bits = tle9104_port_toggle_bits,
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.pin_interrupt_configure = tle9104_pin_interrupt_configure,
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};
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static int tle9104_init(const struct device *dev)
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{
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const struct tle9104_config *config = dev->config;
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struct tle9104_data *data = dev->data;
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uint8_t register_cfg;
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uint8_t register_globalstatus;
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uint8_t register_icvid;
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enum tle9104_register read_reg;
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int result;
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LOG_DBG("initialize TLE9104 instance %s", dev->name);
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result = k_mutex_init(&data->lock);
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if (result != 0) {
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LOG_ERR("unable to initialize mutex");
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return result;
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}
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if (!spi_is_ready_dt(&config->bus)) {
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LOG_ERR("SPI bus %s is not ready", config->bus.bus->name);
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return -ENODEV;
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}
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register_cfg = 0x00;
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for (int i = 0; i < TLE9104_GPIO_COUNT; ++i) {
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const struct gpio_dt_spec *current = config->gpio_control + i;
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if (current->port == NULL) {
|
||||
LOG_DBG("got no control port for output %i, will control it via SPI", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
register_cfg |= TLE9104_CFG_OUT1DD_BIT << i;
|
||||
|
||||
if (!device_is_ready(current->port)) {
|
||||
LOG_ERR("control GPIO %s is not ready", current->port->name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
result = gpio_pin_configure_dt(current, GPIO_OUTPUT_INACTIVE);
|
||||
if (result != 0) {
|
||||
LOG_ERR("failed to initialize control GPIO %i", i);
|
||||
return result;
|
||||
}
|
||||
}
|
||||
|
||||
if (config->gpio_enable.port != NULL) {
|
||||
if (!device_is_ready(config->gpio_enable.port)) {
|
||||
LOG_ERR("enable GPIO %s is not ready", config->gpio_enable.port->name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
result = gpio_pin_configure_dt(&config->gpio_enable, GPIO_OUTPUT_ACTIVE);
|
||||
if (result != 0) {
|
||||
LOG_ERR("failed to enable TLE9104");
|
||||
return result;
|
||||
}
|
||||
}
|
||||
|
||||
result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
|
||||
if (result != 0) {
|
||||
LOG_ERR("failed to initialize GPIO for reset");
|
||||
return result;
|
||||
}
|
||||
|
||||
k_busy_wait(TLE9104_RESET_DURATION_TIME_US);
|
||||
gpio_pin_set_dt(&config->gpio_reset, 0);
|
||||
k_busy_wait(TLE9104_RESET_DURATION_WAIT_TIME_US +
|
||||
TLE9104_RESET_DURATION_WAIT_TIME_SAFETY_MARGIN_US);
|
||||
|
||||
/*
|
||||
* The first read value should be the ICVID, this acts also as the setup of the
|
||||
* global status register address.
|
||||
*/
|
||||
result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_GLOBALSTATUS, 0x00, &read_reg,
|
||||
®ister_icvid);
|
||||
if (result != 0) {
|
||||
return result;
|
||||
}
|
||||
|
||||
if (read_reg != TLE9104REGISTER_ICVID) {
|
||||
LOG_ERR("expected to read register ICVID, got instead 0x%02X", read_reg);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (register_icvid != TLE9104_ICVERSIONID) {
|
||||
LOG_ERR("got unexpected IC version id 0x%02X", register_icvid);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_GLOBALSTATUS, 0x00, &read_reg,
|
||||
®ister_globalstatus);
|
||||
if (result != 0) {
|
||||
return result;
|
||||
}
|
||||
|
||||
if (read_reg != TLE9104REGISTER_GLOBALSTATUS) {
|
||||
LOG_ERR("expected to read register GLOBALSTATUS, got instead 0x%02X", read_reg);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if ((register_globalstatus & TLE9104_GLOBALSTATUS_POR_LATCH_BIT) == 0) {
|
||||
LOG_ERR("no power on reset detected");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
result = tle9104_write_register(dev, TLE9104REGISTER_CFG, register_cfg);
|
||||
if (result != 0) {
|
||||
LOG_ERR("unable to write configuration");
|
||||
return result;
|
||||
}
|
||||
|
||||
register_globalstatus = 0x00;
|
||||
/* disable communication watchdog */
|
||||
tle9104_set_cfg_cwdtime(®ister_cfg, 0);
|
||||
/* enable outputs */
|
||||
register_globalstatus |= TLE9104_GLOBALSTATUS_OUTEN_BIT;
|
||||
|
||||
result = tle9104_write_register(dev, TLE9104REGISTER_GLOBALSTATUS, register_globalstatus);
|
||||
if (result != 0) {
|
||||
LOG_ERR("unable to write global status");
|
||||
return result;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
BUILD_ASSERT(CONFIG_GPIO_TLE9104_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY,
|
||||
"TLE9104 must be initialized after SPI");
|
||||
|
||||
#define TLE9104_INIT_GPIO_FIELDS(inst, gpio) \
|
||||
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, gpio), \
|
||||
(GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), gpio, 0)), ({0}))
|
||||
|
||||
#define TLE9104_INIT(inst) \
|
||||
static const struct tle9104_config tle9104_##inst##_config = { \
|
||||
.common = { \
|
||||
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
|
||||
}, \
|
||||
.bus = SPI_DT_SPEC_INST_GET( \
|
||||
inst, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
|
||||
.gpio_enable = TLE9104_INIT_GPIO_FIELDS(inst, en_gpios), \
|
||||
.gpio_reset = GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), resn_gpios, 0), \
|
||||
.gpio_control = { \
|
||||
TLE9104_INIT_GPIO_FIELDS(inst, in1_gpios), \
|
||||
TLE9104_INIT_GPIO_FIELDS(inst, in2_gpios), \
|
||||
TLE9104_INIT_GPIO_FIELDS(inst, in3_gpios), \
|
||||
TLE9104_INIT_GPIO_FIELDS(inst, in4_gpios), \
|
||||
}, \
|
||||
}; \
|
||||
\
|
||||
static struct tle9104_data tle9104_##inst##_drvdata; \
|
||||
\
|
||||
/* This has to be initialized after the SPI peripheral. */ \
|
||||
DEVICE_DT_INST_DEFINE(inst, tle9104_init, NULL, &tle9104_##inst##_drvdata, \
|
||||
&tle9104_##inst##_config, POST_KERNEL, \
|
||||
CONFIG_GPIO_TLE9104_INIT_PRIORITY, &api_table);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(TLE9104_INIT)
|
||||
Loading…
Reference in a new issue