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dts: riscv: introduce Polarfire SOC QSPI interface

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Add support for the Microchip Polarfire SOC QSPI interface.

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
This commit is contained in:
Naga Sureshkumar Relli 2022-04-12 11:59:36 +05:30 committed by Carles Cufí
parent 41dc7db2d3
commit bfbcb3973a
2 changed files with 40 additions and 7 deletions
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15
dts/bindings/spi/microchip,mpfs-qspi.yaml Normal file
View file

@ -0,0 +1,15 @@
# Copyright (c) 2022 Microchip Technology Inc.
# SPDX-License-Identifier: Apache-2.0
description: Microchip Polarfire SOC QSPI IP node
compatible: "microchip,mpfs-qspi"
include: spi-controller.yaml
properties:
reg:
required: true
interrupts:
required: true

28
dts/riscv/mpfs-icicle.dtsi
View file

@ -15,18 +15,22 @@
clock-frequency = <0>;
compatible = "microsemi,miv", "riscv";
device_type = "cpu";
reg = < 0x01 >;
reg = < 0x0 >;
riscv,isa = "rv64imac";
#status = "disabled";
hlic0: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu@1 {
clock-frequency = <0>;
compatible = "microsemi,miv", "riscv";
device_type = "cpu";
reg = < 0x00 >;
reg = < 0x1 >;
riscv,isa = "rv64imafdc";
hlic: interrupt-controller {
hlic1: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
@ -52,9 +56,11 @@
plic: interrupt-controller@c000000 {
#interrupt-cells = <2>;
#address-cells = <1>;
compatible = "sifive,plic-1.0.0";
interrupt-controller;
interrupts-extended = <&hlic 11>;
interrupts-extended = <&hlic0 11
&hlic1 11>;
reg = <0x0c000000 0x00002000
0x0c002000 0x001fe000
0x0c200000 0x3e000000>;
@ -74,5 +80,17 @@
reg-shift = <2>;
status = "disabled";
};
qspi0: qspi@21000000 {
compatible = "microchip,mpfs-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x21000000 0x1000>;
interrupt-parent = <&plic>;
interrupts = <85 1>;
status = "disabled";
label = "QSPI_0";
clock-frequency = <150000000>;
};
};
};