drivers: cache: Cache driver for NXP XCACHE controller

Some NXP SoC's have External cache that is managed by
the XCACHE cache controller.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

drivers/cache/CMakeLists.txt

@@ -9,3 +9,4 @@ zephyr_library_sources_ifdef(CONFIG_CACHE_ASPEED	cache_aspeed.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_ANDES 	cache_andes.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE		cache_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_NRF_CACHE	cache_nrf.c)
+zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_XCACHE	cache_nxp_xcache.c)

drivers/cache/Kconfig

@@ -21,5 +21,6 @@ comment "Device Drivers"
 source "drivers/cache/Kconfig.aspeed"
 source "drivers/cache/Kconfig.nrf"
 source "drivers/cache/Kconfig.andes"
+source "drivers/cache/Kconfig.nxp_xcache"
 
 endif # CACHE

drivers/cache/Kconfig.nxp_xcache

@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config CACHE_NXP_XCACHE
+	bool "NXP external cache driver for xcache controller"
+	default y
+	select CACHE_HAS_DRIVER
+	depends on HAS_MCUX_XCACHE
+	help
+	  This option enables the XCACHE driver for NXP SOC's.

drivers/cache/cache_nxp_xcache.c

@@ -0,0 +1,125 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/cache.h>
+#include <zephyr/logging/log.h>
+#include <soc.h>
+#include <fsl_cache.h>
+
+LOG_MODULE_REGISTER(cache_nxp_xcache, CONFIG_CACHE_LOG_LEVEL);
+
+#if !defined(NXP_XCACHE_INSTR)
+#define NXP_XCACHE_INSTR XCACHE_PC
+#endif
+
+#if !defined(NXP_XCACHE_DATA)
+#define NXP_XCACHE_DATA XCACHE_PS
+#endif
+
+void cache_data_enable(void)
+{
+	XCACHE_EnableCache(NXP_XCACHE_DATA);
+}
+
+void cache_data_disable(void)
+{
+	XCACHE_DisableCache(NXP_XCACHE_DATA);
+}
+
+int cache_data_flush_all(void)
+{
+	XCACHE_CleanCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_invd_all(void)
+{
+	XCACHE_InvalidateCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_flush_and_invd_all(void)
+{
+	XCACHE_CleanInvalidateCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_flush_range(void *addr, size_t size)
+{
+	XCACHE_CleanCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_data_invd_range(void *addr, size_t size)
+{
+	XCACHE_InvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_data_flush_and_invd_range(void *addr, size_t size)
+{
+	XCACHE_CleanInvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+void cache_instr_enable(void)
+{
+	XCACHE_EnableCache(NXP_XCACHE_INSTR);
+}
+
+void cache_instr_disable(void)
+{
+	XCACHE_DisableCache(NXP_XCACHE_INSTR);
+}
+
+int cache_instr_flush_all(void)
+{
+	XCACHE_CleanCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_invd_all(void)
+{
+	XCACHE_InvalidateCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_flush_and_invd_all(void)
+{
+	XCACHE_CleanInvalidateCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_flush_range(void *addr, size_t size)
+{
+	XCACHE_CleanCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_instr_invd_range(void *addr, size_t size)
+{
+	XCACHE_InvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_instr_flush_and_invd_range(void *addr, size_t size)
+{
+	XCACHE_CleanInvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}

modules/Kconfig.mcux

@@ -364,6 +364,11 @@ config HAS_MCUX_XBARA
 	help
 	  Set if the XBARA module is present on the SoC.
 
+config HAS_MCUX_XCACHE
+	bool
+	help
+	  Set if the XCACHE module is present on the SoC.
+
 config HAS_NXP_MONOLITHIC_NBU
 	bool
 	help