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dts: riscv: microsemi-miv: define CLINT

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The SoC seems to embed a CLINT instance, defined at 0x44000000.

Ref. https://github.com/Mi-V-Soft-RISC-V/platform/blob/main/
miv_rv32_hal/miv_rv32_hal.h

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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Gerard Marull-Paretas 2022-07-28 16:37:28 +02:00 committed by Carles Cufí
parent 0da2ebc7e2
commit c17ee81af4
1 changed files with 6 additions and 0 deletions
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6
dts/riscv/microsemi/microsemi-miv.dtsi
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@ -42,6 +42,12 @@
reg = <0x80040000 0x40000>;
};
clint: clint@44000000 {
compatible = "sifive,clint0";
interrupts-extended = <&hlic 3>, <&hlic 7>;
reg = <0x44000000 0x10000>;
};
plic: interrupt-controller@40000000 {
compatible = "sifive,plic-1.0.0";
#address-cells = <0>;