soc: add nRF54L15 FLPR core support

Add support for nRF54L15 FLPR core.

Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>

soc/nordic/common/Kconfig.peripherals

@@ -72,6 +72,9 @@ config HAS_HW_NRF_GPIO0
 config HAS_HW_NRF_GPIO1
 	def_bool $(dt_nodelabel_enabled_with_compat,gpio1,$(DT_COMPAT_NORDIC_NRF_GPIO))
 
+config HAS_HW_NRF_GPIO2
+	def_bool $(dt_nodelabel_enabled_with_compat,gpio2,$(DT_COMPAT_NORDIC_NRF_GPIO))
+
 config HAS_HW_NRF_GPIOTE0
 	def_bool $(dt_nodelabel_enabled_with_compat,gpiote0,$(DT_COMPAT_NORDIC_NRF_GPIOTE))
 

soc/nordic/nrf54l/Kconfig

@@ -19,6 +19,9 @@ config SOC_NRF54L15_ENGA_CPUAPP
 	select HAS_HW_NRF_RADIO_IEEE802154
 	select HAS_POWEROFF
 
+config SOC_NRF54L15_ENGA_CPUFLPR
+	depends on RISCV_CORE_NORDIC_VPR
+
 if SOC_SERIES_NRF54LX
 
 config SOC_NRF54LX_SKIP_CLOCK_CONFIG

soc/nordic/nrf54l/Kconfig.defconfig

@@ -7,10 +7,26 @@ if SOC_SERIES_NRF54LX
 
 rsource "Kconfig.defconfig.nrf54l*"
 
+if ARM
+
 config CORTEX_M_SYSTICK
 	default !NRF_GRTC_TIMER
 
 config CACHE_NRF_CACHE
 	default y if EXTERNAL_CACHE
 
+endif # ARM
+
+if RISCV
+
+DT_CHOSEN_Z_SRAM = zephyr,sram
+DT_CHOSEN_Z_CODE = zephyr,code-partition
+
+config BUILD_OUTPUT_ADJUST_LMA
+	depends on !XIP
+	default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \
+		 $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))"
+
+endif # RISCV
+
 endif # SOC_SERIES_NRF54LX

soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuflpr

@@ -0,0 +1,15 @@
+# Nordic Semiconductor nRF54L15 MCU
+
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF54L15_ENGA_CPUFLPR
+
+config RISCV_HAS_CPU_IDLE
+	bool
+
+config NUM_IRQS
+	int
+	default 287
+
+endif # SOC_NRF54L15_ENGA_CPUFLPR

soc/nordic/nrf54l/Kconfig.soc

@@ -21,5 +21,11 @@ config SOC_NRF54L15_ENGA_CPUAPP
 	help
 	  NRF54L15 ENGA CPUAPP
 
+config SOC_NRF54L15_ENGA_CPUFLPR
+	bool
+	select SOC_NRF54L15_ENGA
+	help
+	  NRF54L15 ENGA CPUFLPR
+
 config SOC
 	default "nrf54l15" if SOC_NRF54L15

soc/nordic/nrf54l/soc.c

@@ -18,19 +18,23 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/cache.h>
 
+#if defined(NRF_APPLICATION)
 #include <cmsis_core.h>
 #include <hal/nrf_glitchdet.h>
 #include <hal/nrf_oscillators.h>
 #include <hal/nrf_power.h>
 #include <hal/nrf_regulators.h>
+#endif
 #include <soc/nrfx_coredep.h>
 
 #include <system_nrf54l.h>
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
+#if defined(NRF_APPLICATION)
 #define LFXO_NODE DT_NODELABEL(lfxo)
 #define HFXO_NODE DT_NODELABEL(hfxo)
+#endif
 
 static int nordicsemi_nrf54l_init(void)
 {
@@ -39,6 +43,7 @@ static int nordicsemi_nrf54l_init(void)
 	 */
 	SystemCoreClockUpdate();
 
+#if defined(NRF_APPLICATION)
 	/* Enable ICACHE */
 	sys_cache_instr_enable();
 
@@ -120,6 +125,7 @@ static int nordicsemi_nrf54l_init(void)
 #if defined(CONFIG_ELV_GRTC_LFXO_ALLOWED)
 	nrf_regulators_elv_mode_allow_set(NRF_REGULATORS, NRF_REGULATORS_ELV_ELVGRTCLFXO_MASK);
 #endif /* CONFIG_ELV_GRTC_LFXO_ALLOWED */
+#endif /* NRF_APPLICATION */
 
 	return 0;
 }

soc/nordic/soc.yml

@@ -24,6 +24,7 @@ family:
     - name: nrf54l15
       cpuclusters:
       - name: cpuapp
+      - name: cpuflpr
   - name: nrf54h
     socs:
     - name: nrf54h20

soc/nordic/validate_base_addresses.c

@@ -310,6 +310,10 @@ CHECK_DT_REG(uicr, NRF_UICR);
 CHECK_DT_REG(usbd, NRF_USBD);
 CHECK_DT_REG(usbreg, NRF_USBREGULATOR);
 CHECK_DT_REG(vmc, NRF_VMC);
+CHECK_DT_REG(cpuflpr_clic, NRF_FLPR_VPRCLIC);
+#if defined(CONFIG_SOC_NRF54L15)
+CHECK_DT_REG(cpuflpr_vpr, NRF_VPR00);
+#endif
 CHECK_DT_REG(wdt, NRF_WDT0);	/* this should be the same node as wdt0 */
 CHECK_DT_REG(wdt0, NRF_WDT0);
 CHECK_DT_REG(wdt1, NRF_WDT1);

soc/nordic/validate_rram_partitions.c

@@ -43,7 +43,7 @@
 
 /* clang-format off */
 
-#define RRAM_BASE REG_ADDR_NS(DT_NODELABEL(rram0))
+#define RRAM_BASE REG_ADDR_NS(DT_CHOSEN(zephyr_flash))
 #define RRAM_CONTROLLER DT_NODELABEL(rram_controller)
 
 #if !DT_NODE_EXISTS(RRAM_CONTROLLER)