From c42ef7117dc97c43476f5cb278045fed10f0a37f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Tue, 16 Jan 2024 15:04:03 +0100 Subject: [PATCH] dts: riscv: sifive: fu540: add missing ngpios property FU540 SoC has 16 GPIOs, this way, the GPIO API can perform correct asserts when a pin is provided. Note that default is 32, correct for eg FE310. Signed-off-by: Gerard Marull-Paretas --- dts/riscv/sifive/riscv64-fu540.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/dts/riscv/sifive/riscv64-fu540.dtsi b/dts/riscv/sifive/riscv64-fu540.dtsi index ed56401d462..ebb60e03aae 100644 --- a/dts/riscv/sifive/riscv64-fu540.dtsi +++ b/dts/riscv/sifive/riscv64-fu540.dtsi @@ -179,6 +179,7 @@ gpio0: gpio@10060000 { compatible = "sifive,gpio0"; gpio-controller; + ngpios = <16>; interrupt-parent = <&plic>; interrupts = <7 1>, <8 1>, <9 1>, <10 1>, <11 1>, <12 1>, <13 1>, <14 1>,