soc: st: move init code from SYS_INIT to hooks

Replace SYS_INIT with SoC hooks and adapt SoC init code

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

soc/st/stm32/stm32c0x/Kconfig

@@ -11,3 +11,4 @@ config SOC_SERIES_STM32C0X
 	select HAS_STM32CUBE
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_POWEROFF
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32c0x/soc.c

@@ -22,11 +22,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32c0_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Accelerator I-cache and prefetch */
 	LL_FLASH_EnableInstCache();
@@ -35,8 +32,4 @@ static int stm32c0_init(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 48 MHz from HSI */
 	SystemCoreClock = 48000000;
-
-	return 0;
 }
-
-SYS_INIT(stm32c0_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32f0x/Kconfig

@@ -9,3 +9,4 @@ config SOC_SERIES_STM32F0X
 	select CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_STM32CUBE
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32f0x/soc.c

@@ -61,11 +61,8 @@ void relocate_vector_table(void)
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32f0_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
@@ -73,8 +70,4 @@ static int stm32f0_init(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 8 MHz from HSI */
 	SystemCoreClock = 8000000;
-
-	return 0;
 }
-
-SYS_INIT(stm32f0_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32f1x/Kconfig

@@ -9,3 +9,4 @@ config SOC_SERIES_STM32F1X
 	select CPU_CORTEX_M_HAS_DWT
 	select HAS_STM32CUBE
 	select HAS_SWO
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32f1x/soc.c

@@ -20,11 +20,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32f1_init(void)
+void soc_early_init_hook(void)
 {
 #ifdef FLASH_ACR_PRFTBE
 	/* Enable ART Accelerator prefetch */
@@ -34,8 +31,4 @@ static int stm32f1_init(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 8 MHz from HSI */
 	SystemCoreClock = 8000000;
-
-	return 0;
 }
-
-SYS_INIT(stm32f1_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32f2x/Kconfig

@@ -10,3 +10,4 @@ config SOC_SERIES_STM32F2X
 	select HAS_STM32CUBE
 	select HAS_SWO
 	select CPU_HAS_ARM_MPU
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32f2x/soc.c

@@ -23,11 +23,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32f2_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Flash I/D-cache accelerator and prefetch */
 	LL_FLASH_EnableInstCache();
@@ -37,8 +34,4 @@ static int stm32f2_init(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
-
-	return 0;
 }
-
-SYS_INIT(stm32f2_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32f3x/Kconfig

@@ -10,3 +10,4 @@ config SOC_SERIES_STM32F3X
 	select CPU_HAS_FPU
 	select HAS_STM32CUBE
 	select HAS_SWO
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32f3x/soc.c

@@ -19,11 +19,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32f3_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
@@ -34,8 +31,4 @@ static int stm32f3_init(void)
 
 	/* Allow reflashing the board */
 	LL_DBGMCU_EnableDBGSleepMode();
-
-	return 0;
 }
-
-SYS_INIT(stm32f3_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32f4x/Kconfig

@@ -12,3 +12,4 @@ config SOC_SERIES_STM32F4X
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select HAS_PM
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32f4x/power.c

@@ -75,15 +75,10 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 	irq_unlock(0);
 }
 
-static int stm32_power_init(void)
+void stm32_power_init(void)
 {
 	/* Enable Power clock. It should by done by default, but make sure to
 	 * enable it for all STM32F4x chips.
 	 */
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-	/* Enabling debug during STOP mode is done by the common STM32 configuration */
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32f4x/soc.c

@@ -16,15 +16,14 @@
 #include <cmsis_core.h>
 #include <stm32_ll_system.h>
 
+extern void stm32_power_init(void);
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int st_stm32f4_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Flash I/D-cache and prefetch */
 	LL_FLASH_EnablePrefetch();
@@ -34,8 +33,7 @@ static int st_stm32f4_init(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
-
-	return 0;
+#if CONFIG_PM
+	stm32_power_init();
+#endif
 }
-
-SYS_INIT(st_stm32f4_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32f7x/Kconfig

@@ -13,3 +13,4 @@ config SOC_SERIES_STM32F7X
 	select HAS_STM32CUBE
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32f7x/soc.c

@@ -22,11 +22,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int st_stm32f7_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Flash cache accelerator and prefetch */
 	LL_FLASH_EnableART();
@@ -38,8 +35,4 @@ static int st_stm32f7_init(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
-
-	return 0;
 }
-
-SYS_INIT(st_stm32f7_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32g0x/Kconfig

@@ -12,3 +12,4 @@ config SOC_SERIES_STM32G0X
 	select HAS_STM32CUBE
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_PM
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32g0x/power.c

@@ -81,13 +81,9 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_power_init(void)
 {
 
 	/* enable Power clock */
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32g0x/soc.c

@@ -71,15 +71,14 @@ static void stm32g0_disable_dead_battery(void)
 #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
 }
 
+extern void stm32_power_init(void);
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32g0_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Accelerator I-cache and prefetch */
 	LL_FLASH_EnableInstCache();
@@ -91,8 +90,7 @@ static int stm32g0_init(void)
 
 	/* Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */
 	stm32g0_disable_dead_battery();
-
-	return 0;
+#if CONFIG_PM
+	stm32_power_init();
+#endif
 }
-
-SYS_INIT(stm32g0_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32g4x/Kconfig

@@ -12,3 +12,4 @@ config SOC_SERIES_STM32G4X
 	select CPU_HAS_ARM_MPU
 	select HAS_PM
 	select HAS_SWO
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32g4x/power.c

@@ -79,13 +79,9 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_power_init(void)
 {
 
 	/* enable Power clock */
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32g4x/soc.c

@@ -24,11 +24,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32g4_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Accelerator I/D-cache and prefetch */
 	LL_FLASH_EnableInstCache();
@@ -51,7 +48,7 @@ static int stm32g4_init(void)
 	}
 
 #endif /* PWR_CR3_UCPD_DBDIS */
-	return 0;
+#if CONFIG_PM
+	stm32_power_init();
+#endif
 }
-
-SYS_INIT(stm32g4_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32h5x/Kconfig

@@ -15,3 +15,4 @@ config SOC_SERIES_STM32H5X
 	select HAS_STM32CUBE
 	select HAS_SWO
 	select HAS_PM
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32h5x/power.c

@@ -68,9 +68,6 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_power_init(void)
 {
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32h5x/soc.c

@@ -21,15 +21,13 @@
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
+extern void stm32_power_init(void);
 /**
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32h5_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable instruction cache in 1-way (direct mapped cache) */
 	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
@@ -47,7 +45,8 @@ static int stm32h5_init(void)
 	}
 
 #endif /* PWR_UCPDR_UCPD_DBDIS */
-	return 0;
-}
 
-SYS_INIT(stm32h5_init, PRE_KERNEL_1, 0);
+#if CONFIG_PM
+	stm32_power_init();
+#endif
+}

soc/st/stm32/stm32h7rsx/Kconfig

@@ -14,3 +14,4 @@ config SOC_SERIES_STM32H7RSX
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32h7rsx/soc.c

@@ -25,11 +25,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32h7rs_init(void)
+void soc_early_init_hook(void)
 {
 	sys_cache_instr_enable();
 	sys_cache_data_enable();
@@ -71,8 +68,4 @@ static int stm32h7rs_init(void)
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
 	while (LL_PWR_IsActiveFlag_VOSRDY() == 0) {
 	}
-
-	return 0;
 }
-
-SYS_INIT(stm32h7rs_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32h7x/Kconfig

@@ -15,6 +15,7 @@ config SOC_SERIES_STM32H7X
 	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
 	select CPU_HAS_ICACHE if CPU_CORTEX_M7
 	select CPU_HAS_DCACHE if CPU_CORTEX_M7
+	select SOC_EARLY_INIT_HOOK
 
 config SOC_STM32H723XX
 	select CPU_CORTEX_M7

soc/st/stm32/stm32h7x/soc_m4.c

@@ -26,11 +26,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32h7_m4_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Flash cache accelerator */
 	LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ART);
@@ -55,8 +52,4 @@ static int stm32h7_m4_init(void)
 			;
 		}
 	}
-
-	return 0;
 }
-
-SYS_INIT(stm32h7_m4_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32h7x/soc_m7.c

@@ -49,11 +49,8 @@ static int stm32h7_m4_wakeup(void)
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32h7_init(void)
+void soc_early_init_hook(void)
 {
 	sys_cache_instr_enable();
 	sys_cache_data_enable();
@@ -105,13 +102,8 @@ static int stm32h7_init(void)
 	if (LL_DBGMCU_GetRevisionID() == 0x1003) {
 		MODIFY_REG(GPV->AXI_TARG7_FN_MOD, 0x1, 0x1);
 	}
-
-	return 0;
 }
 
-SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);
-
-
 #if defined(CONFIG_STM32H7_DUAL_CORE)
 /* Unlock M4 once system configuration has been done */
 SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);

soc/st/stm32/stm32l0x/Kconfig

@@ -10,6 +10,7 @@ config SOC_SERIES_STM32L0X
 	select HAS_STM32CUBE
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_PM
+	select SOC_EARLY_INIT_HOOK
 
 config SOC_STM32L051XX
 	select CPU_HAS_ARM_MPU

soc/st/stm32/stm32l0x/power.c

@@ -74,13 +74,9 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void soc_early_init_hook(void)
 {
 
 	/* Enable Power clock */
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32l0x/soc.c

@@ -22,11 +22,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32l0_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
@@ -43,8 +40,4 @@ static int stm32l0_init(void)
 	 * https://github.com/zephyrproject-rtos/zephyr/issues/#34324 )
 	 */
 	LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
-
-	return 0;
 }
-
-SYS_INIT(stm32l0_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32l1x/Kconfig

@@ -10,3 +10,4 @@ config SOC_SERIES_STM32L1X
 	select HAS_STM32CUBE
 	select HAS_SWO
 	select CPU_HAS_ARM_MPU
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32l1x/soc.c

@@ -23,11 +23,8 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32l1_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
@@ -42,8 +39,4 @@ static int stm32l1_init(void)
 	 */
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
-
-	return 0;
 }
-
-SYS_INIT(stm32l1_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32l4x/Kconfig

@@ -14,3 +14,4 @@ config SOC_SERIES_STM32L4X
 	select HAS_SWO
 	select HAS_PM
 	select HAS_POWEROFF
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32l4x/power.c

@@ -114,13 +114,9 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_power_init(void)
 {
 
 	/* enable Power clock */
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32l4x/soc.c

@@ -20,16 +20,13 @@
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
-
+extern void stm32_power_init(void);
 /**
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32l4_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable the ART Accelerator I-cache, D-cache and prefetch */
 	LL_FLASH_EnableInstCache();
@@ -39,8 +36,7 @@ static int stm32l4_init(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
 	SystemCoreClock = 4000000;
-
-	return 0;
+#if CONFIG_PM
+	stm32_power_init();
+#endif
 }
-
-SYS_INIT(stm32l4_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32l5x/Kconfig

@@ -14,3 +14,4 @@ config SOC_SERIES_STM32L5X
 	select CPU_CORTEX_M_HAS_DWT
 	select HAS_STM32CUBE
 	select HAS_PM
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32l5x/power.c

@@ -98,13 +98,9 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_power_init(void)
 {
 
 	/* enable Power clock */
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32l5x/soc.c

@@ -21,15 +21,13 @@
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
+extern void stm32_power_init(void);
 /**
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32l5_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ICACHE */
 	while (LL_ICACHE_IsActiveFlag_BUSY()) {
@@ -49,8 +47,7 @@ static int stm32l5_init(void)
 		/* Disable USB Type-C dead battery pull-down behavior */
 		LL_PWR_DisableUCPDDeadBattery();
 	}
-
-	return 0;
+#if CONFIG_PM
+	stm32_power_init();
+#endif
 }
-
-SYS_INIT(stm32l5_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32mp1x/Kconfig

@@ -11,3 +11,4 @@ config SOC_SERIES_STM32MP1X
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select OPENAMP_RSC_TABLE if RAM_CONSOLE
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32mp1x/soc.c

@@ -21,19 +21,12 @@
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32m4_init(void)
+void soc_early_init_hook(void)
 {
 	/*HW semaphore Clock enable*/
 	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	SystemCoreClock = 209000000;
-
-	return 0;
 }
-
-SYS_INIT(stm32m4_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32u0x/Kconfig

@@ -10,3 +10,4 @@ config SOC_SERIES_STM32U0X
 	select CPU_CORTEX_M_HAS_VTOR
 	select HAS_STM32CUBE
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32u0x/soc.c

@@ -24,11 +24,8 @@ LOG_MODULE_REGISTER(soc);
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32u0_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable ART Accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
@@ -38,8 +35,4 @@ static int stm32u0_init(void)
 	SystemCoreClock = 16000000;
 
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-	return 0;
 }
-
-SYS_INIT(stm32u0_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32u5x/Kconfig

@@ -17,6 +17,7 @@ config SOC_SERIES_STM32U5X
 	select HAS_STM32CUBE
 	select HAS_PM
 	select HAS_POWEROFF
+	select SOC_EARLY_INIT_HOOK
 
 config STM32_STOP3_LP_MODE
 	bool

soc/st/stm32/stm32u5x/power.c

@@ -170,7 +170,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_power_init(void)
 {
 
 	/* enable Power clock */
@@ -181,8 +181,4 @@ static int stm32_power_init(void)
 		    pwr_stop3_isr, 0, 0);
 	irq_enable(PWR_S3WU_IRQn);
 #endif
-
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32u5x/soc.c

@@ -21,15 +21,13 @@
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
+extern void stm32_power_init(void);
 /**
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32u5_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable instruction cache in 1-way (direct mapped cache) */
 	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
@@ -57,7 +55,7 @@ static int stm32u5_init(void)
 #error "Unsupported power configuration"
 #endif
 
-	return 0;
+#if CONFIG_PM
+	stm32_power_init();
+#endif
 }
-
-SYS_INIT(stm32u5_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32wbax/Kconfig

@@ -15,3 +15,4 @@ config SOC_SERIES_STM32WBAX
 	select HAS_STM32CUBE
 	select USE_STM32_HAL_PWR_EX
 	select HAS_PM
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32wbax/power.c

@@ -26,7 +26,7 @@
 
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
-static int stm32_power_init(void);
+void stm32_power_init(void);
 
 static void disable_cache(void)
 {
@@ -207,7 +207,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_power_init(void)
 {
 
 #ifdef CONFIG_BT_STM32WBA
@@ -228,8 +228,4 @@ static int stm32_power_init(void)
 	LL_PWR_EnableUltraLowPowerMode();
 
 	LL_FLASH_EnableSleepPowerDown();
-
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32wbax/soc.c

@@ -18,7 +18,7 @@
 #include <zephyr/arch/cpu.h>
 #include <zephyr/irq.h>
 #include <zephyr/logging/log.h>
-
+#include "soc.h"
 #include <cmsis_core.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
@@ -28,11 +28,8 @@ LOG_MODULE_REGISTER(soc);
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-int stm32wba_init(void)
+void stm32wba_init(void)
 {
 	/* Enable instruction cache in 1-way (direct mapped cache) */
 	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
@@ -53,8 +50,12 @@ int stm32wba_init(void)
 #elif defined(CONFIG_POWER_SUPPLY_LDO)
 	LL_PWR_SetRegulatorSupply(LL_PWR_LDO_SUPPLY);
 #endif
-
-	return 0;
 }
 
-SYS_INIT(stm32wba_init, PRE_KERNEL_1, 0);
+void soc_early_init_hook(void)
+{
+	stm32wba_init();
+#if CONFIG_PM
+	stm32_power_init();
+#endif
+}

soc/st/stm32/stm32wbax/soc.h

@@ -17,8 +17,11 @@
 
 #include <stm32wbaxx.h>
 
+
 /* function exported to the soc power.c */
-int stm32wba_init(void);
+void stm32wba_init(void);
+
+void stm32_power_init(void);
 
 #endif /* !_ASMLANGUAGE */
 

soc/st/stm32/stm32wbx/Kconfig

@@ -13,3 +13,4 @@ config SOC_SERIES_STM32WBX
 	select HAS_SWO
 	select HAS_PM
 	select HAS_POWEROFF
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32wbx/power.c

@@ -139,9 +139,6 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_pm_init(void)
 {
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32wbx/soc.c

@@ -20,15 +20,13 @@
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
+extern void stm32_pm_init(void);
 /**
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32wb_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable the ART Accelerator I-cache, D-cache and prefetch */
 	LL_FLASH_EnableInstCache();
@@ -42,8 +40,8 @@ static int stm32wb_init(void)
 	/* Set C2 Power Mode to shutdown */
 	/* It will be updated by C2 when required */
 	LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
+#if CONFIG_PM
+	stm32_pm_init();
+#endif
 
-	return 0;
 }
-
-SYS_INIT(stm32wb_init, PRE_KERNEL_1, 0);

soc/st/stm32/stm32wlx/Kconfig

@@ -11,3 +11,4 @@ config SOC_SERIES_STM32WLX
 	select CPU_HAS_ARM_MPU
 	select HAS_PM
 	select HAS_POWEROFF
+	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32wlx/power.c

@@ -83,9 +83,6 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 }
 
 /* Initialize STM32 Power */
-static int stm32_power_init(void)
+void stm32_pm_init(void)
 {
-	return 0;
 }
-
-SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32wlx/soc.c

@@ -21,16 +21,13 @@
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
-
+extern void stm32_pm_init(void);
 /**
  * @brief Perform basic hardware initialization at boot.
  *
  * This needs to be run from the very beginning.
- * So the init priority has to be 0 (zero).
- *
- * @return 0
  */
-static int stm32wl_init(void)
+void soc_early_init_hook(void)
 {
 	/* Enable CPU data and instruction cache and prefetch */
 	LL_FLASH_EnableInstCache();
@@ -40,8 +37,7 @@ static int stm32wl_init(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
 	SystemCoreClock = 4000000;
-
-	return 0;
+#if CONFIG_PM
+	stm32_pm_init();
+#endif
 }
-
-SYS_INIT(stm32wl_init, PRE_KERNEL_1, 0);