adafruit-mirror/zephyr
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 9

mtl: dts: add L3 memory definitions macros

Browse source 
Add helper macros for l3 memory definitions from
the Device Tree

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
This commit is contained in:
Marcin Szkudlinski 2022-11-15 21:57:10 +01:00 committed by Anas Nashif
parent 5801ab2231
commit c929bbcc58
1 changed files with 36 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h
View file

@ -24,6 +24,13 @@
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* L3 region (IMR), located in host memory */
#define L3_MEM_BASE_ADDR (DT_REG_ADDR(DT_NODELABEL(imr1)))
#define L3_MEM_SIZE (DT_REG_SIZE(DT_NODELABEL(imr1)))
#define L3_MEM_PAGE_SIZE (DT_PROP(DT_NODELABEL(imr1), block_size))
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,
@ -31,14 +38,39 @@
* memory. There's no ability to change this offset, it's a magic
* number from rimage we simply need to honor.
*/
#define IMR_BOOT_LDR_MANIFEST_OFFSET 0x42000
#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
#define IMR_BOOT_LDR_MANIFEST_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_MANIFEST_OFFSET)
#define IMR_BOOT_LDR_DATA_BASE (0xA1048000+0x1000)
#define IMR_BOOT_LDR_MANIFEST_BASE 0xA1042000
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x180
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + IMR_BOOT_LDR_MANIFEST_SIZE)
#define IMR_BOOT_LDR_LIT_SIZE 0x40
#define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \
IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
#define IMR_BOOT_LDR_TEXT_SIZE 0x1C00
#define IMR_BOOT_LDR_TEXT_BASE (IMR_BOOT_LDR_LIT_BASE + IMR_BOOT_LDR_LIT_SIZE)
#define IMR_BOOT_LDR_DATA_OFFSET 0x49000
#define IMR_BOOT_LDR_DATA_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_DATA_OFFSET)
#define IMR_BOOT_LDR_DATA_SIZE 0xA8000
#define IMR_BOOT_LDR_BSS_OFFSET 0x110000
#define IMR_BOOT_LDR_BSS_BASE (L3_MEM_BASE_ADDR + IMR_BOOT_LDR_BSS_OFFSET)
#define IMR_BOOT_LDR_BSS_SIZE 0x10000
/* stack to be used at boot, when RAM is not yet powered up */
#define IMR_BOOT_LDR_STACK_BASE (IMR_BOOT_LDR_BSS_BASE + IMR_BOOT_LDR_BSS_SIZE)
#define IMR_BOOT_LDR_STACK_SIZE 0x1000
/* position of L3 heap, size of L3 heap - till end of the L3 memory */
#define IMR_L3_HEAP_BASE (IMR_BOOT_LDR_STACK_BASE + IMR_BOOT_LDR_STACK_SIZE)
#define IMR_L3_HEAP_SIZE (L3_MEM_SIZE - \
(IMR_L3_HEAP_BASE - L3_MEM_BASE_ADDR))
#define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
/* L1 init */
#define ADSP_L1CC_ADDR (0x1FE80080)
#define ADSP_CxL1CCAP_ADDR (ADSP_L1CC_ADDR + 0x0000)