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dts: riscv: andes_v5: update andes_v5_ae350.dtsi

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Fix mtimer lack of interrupts-extended and make syscon compatilbe to
atcsmu100.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng 2023-06-19 11:24:13 +08:00 committed by Fabio Baltieri
parent ea2aac6e51
commit ca72a0a47f
1 changed files with 4 additions and 2 deletions
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6
dts/riscv/andes/andes_v5_ae350.dtsi
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@ -201,11 +201,13 @@
compatible = "andestech,machine-timer";
reg = <0xe6000000 0x10>;
interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7
&CPU2_intc 7 &CPU3_intc 7>;
&CPU2_intc 7 &CPU3_intc 7
&CPU4_intc 7 &CPU5_intc 7
&CPU6_intc 7 &CPU7_intc 7>;
};
syscon: syscon@f0100000 {
compatible = "syscon";
compatible = "syscon", "andestech,atcsmu100";
reg = <0xf0100000 0x1000>;
status = "disabled";
};