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dts: riscv: Fix a typo in riscv,isa for mpfs

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The RISC-V ISA extension is called `Zifencei` instead of `Zfencei`.

Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
This commit is contained in:
Mateusz Holenko 2023-12-11 18:17:51 +01:00 committed by Henrik Brix Andersen
parent b504932ae9
commit cb677febb1
1 changed files with 1 additions and 1 deletions
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dts/riscv/microchip/mpfs.dtsi
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@ -19,7 +19,7 @@
compatible = "riscv";
device_type = "cpu";
reg = < 0x0 >;
riscv,isa = "rv64imac_zicsr_zfencei";
riscv,isa = "rv64imac_zicsr_zifencei";
hlic0: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;