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dts: x86: intel: alder_lake: Added SPI instances

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Added SPI instances supported on Alderlake platform

Signed-off-by: Bindu S <bindu.s@intel.com>
This commit is contained in:
Bindu S 2023-08-23 09:15:53 +05:30 committed by Carles Cufí
parent 72c94d982c
commit cb6aef4329
1 changed files with 48 additions and 0 deletions
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48
dts/x86/intel/alder_lake.dtsi
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@ -180,6 +180,54 @@
status = "disabled";
};
spi0: spi0 {
compatible = "intel,penwell-spi";
vendor-id = <0x8086>;
device-id = <0x54aa>;
#address-cells = <1>;
#size-cells = <0>;
pw,cs-mode = <0>;
pw,cs-output = <0>;
pw,fifo-depth = <64>;
cs-gpios = <&gpio_4_e 10 GPIO_ACTIVE_LOW>;
clock-frequency = <100000000>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
};
spi1: spi1 {
compatible = "intel,penwell-spi";
vendor-id = <0x8086>;
device-id = <0x54ab>;
#address-cells = <1>;
#size-cells = <0>;
pw,cs-mode = <0>;
pw,cs-output = <0>;
pw,fifo-depth = <64>;
cs-gpios = <&gpio_4_f 16 GPIO_ACTIVE_LOW>;
clock-frequency = <100000000>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "disabled";
};
spi2: spi2 {
compatible = "intel,penwell-spi";
vendor-id = <0x8086>;
device-id = <0x54fb>;
#address-cells = <1>;
#size-cells = <0>;
pw,cs-mode = <0>;
pw,cs-output = <0>;
pw,fifo-depth = <64>;
cs-gpios = <&gpio_1_d 9 GPIO_ACTIVE_LOW>;
clock-frequency = <100000000>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "disabled";
};
};
soc {