drivers: memc: add memc_mcux_flexspi_aps6404l driver
Add driver for aps6404l PSRAM, using FlexSPI MEMC driver interface. Signed-off-by: David Missael Maciel <davidmissael.maciel@nxp.com>
This commit is contained in:
David Missael Maciel
Anas Nashif
parent
e8d9dec141
commit
cc1266ad6a
4 changed files with 283 additions and 0 deletions
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@ -11,6 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c)
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zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_W956A8MBYA memc_mcux_flexspi_w956a8mbya.c)
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zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_S27KS0641 memc_mcux_flexspi_s27ks0641.c)
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zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6408L memc_mcux_flexspi_aps6408l.c)
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zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_APS6404L memc_mcux_flexspi_aps6404l.c)
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zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_IS66WVQ8M4 memc_mcux_flexspi_is66wvq8m4.c)
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zephyr_library_sources_ifdef(CONFIG_MEMC_NXP_FLEXRAM memc_nxp_flexram.c)
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@ -30,6 +30,12 @@ config MEMC_MCUX_FLEXSPI_IS66WVQ8M4
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depends on DT_HAS_NXP_IMX_FLEXSPI_IS66WVQ8M4_ENABLED
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select MEMC_MCUX_FLEXSPI
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config MEMC_MCUX_FLEXSPI_APS6404L
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bool "MCUX FlexSPI AP Memory APS6404L pSRAM driver"
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default y
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depends on DT_HAS_NXP_IMX_FLEXSPI_APS6404L_ENABLED
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select MEMC_MCUX_FLEXSPI
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config MEMC_MCUX_FLEXSPI_INIT_PRIORITY
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int "MCUX FLEXSPI MEMC driver initialization priority"
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default MEMC_INIT_PRIORITY
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268
drivers/memc/memc_mcux_flexspi_aps6404l.c
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268
drivers/memc/memc_mcux_flexspi_aps6404l.c
Normal file
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@ -0,0 +1,268 @@
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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Based on memc_mcux_flexspi_s27ks0641, which is: Copyright 2021 Basalte bv
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*/
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#define DT_DRV_COMPAT nxp_imx_flexspi_aps6404l
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/util.h>
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#include "memc_mcux_flexspi.h"
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/*
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* NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions
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* called while interacting with the flexspi MUST be relocated to SRAM or ITCM
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* at runtime, so that the chip does not access the flexspi to read program
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* instructions while it is being written to
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*/
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#if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_MEMC_LOG_LEVEL > 0)
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#warning "Enabling memc driver logging and XIP mode simultaneously can cause \
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read-while-write hazards. This configuration is not recommended."
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#endif
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LOG_MODULE_REGISTER(memc_flexspi_aps6404l, CONFIG_MEMC_LOG_LEVEL);
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#define APM_VENDOR_ID 0xD
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enum {
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READ_DATA = 0,
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WRITE_DATA,
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RESET_EN,
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RESET,
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READ_ID
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};
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struct memc_flexspi_aps6404l_config {
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flexspi_port_t port;
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flexspi_device_config_t config;
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};
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/* Device variables used in critical sections should be in this structure */
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struct memc_flexspi_aps6404l_data {
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const struct device *controller;
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};
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static const uint32_t memc_flexspi_aps6404l_lut[][4] = {
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/* Read Data (Sync read, linear burst) */
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[READ_DATA] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD,
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0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),
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},
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/* Write Data (Sync write, linear burst) */
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[WRITE_DATA] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x38,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD,
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0x00, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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},
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[RESET_EN] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x66,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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},
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/* Reset (Global reset) */
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[RESET] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x99,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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},
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[READ_ID] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x08,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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};
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static int memc_flexspi_aps6404l_get_vendor_id(const struct device *dev,
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uint8_t *vendor_id)
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{
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const struct memc_flexspi_aps6404l_config *config = dev->config;
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struct memc_flexspi_aps6404l_data *data = dev->data;
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uint32_t buffer = 0;
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int ret;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0x0,
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.port = config->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_ID,
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.data = &buffer,
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.dataSize = 1,
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};
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ret = memc_flexspi_transfer(data->controller, &transfer);
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*vendor_id = buffer & 0x1f;
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return ret;
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}
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static int memc_flexspi_aps6404l_reset_enable(const struct device *dev)
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{
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const struct memc_flexspi_aps6404l_config *config = dev->config;
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struct memc_flexspi_aps6404l_data *data = dev->data;
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int ret;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0x0,
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.port = config->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = RESET_EN,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Enabling reset ram");
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ret = memc_flexspi_transfer(data->controller, &transfer);
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if (ret < 0) {
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return ret;
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}
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/* We need to delay 5 ms to allow APS6404L pSRAM to reinitialize */
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k_msleep(5);
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return ret;
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}
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static int memc_flexspi_aps6404l_reset(const struct device *dev)
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{
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const struct memc_flexspi_aps6404l_config *config = dev->config;
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struct memc_flexspi_aps6404l_data *data = dev->data;
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int ret;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0x0,
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.port = config->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = RESET,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Resetting ram");
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ret = memc_flexspi_transfer(data->controller, &transfer);
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if (ret < 0) {
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return ret;
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}
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/* We need to delay 5 ms to allow APS6404L pSRAM to reinitialize */
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k_msleep(5);
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return ret;
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}
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static int memc_flexspi_aps6404l_init(const struct device *dev)
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{
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const struct memc_flexspi_aps6404l_config *config = dev->config;
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struct memc_flexspi_aps6404l_data *data = dev->data;
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uint8_t vendor_id;
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if (!device_is_ready(data->controller)) {
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LOG_ERR("Controller device not ready");
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return -ENODEV;
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}
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if (memc_flexspi_set_device_config(data->controller, &config->config,
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(const uint32_t *) memc_flexspi_aps6404l_lut,
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sizeof(memc_flexspi_aps6404l_lut) / MEMC_FLEXSPI_CMD_SIZE,
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config->port)) {
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LOG_ERR("Could not set device configuration");
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return -EINVAL;
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}
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memc_flexspi_reset(data->controller);
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if (memc_flexspi_aps6404l_reset_enable(dev)) {
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LOG_ERR("Could not enable reset pSRAM");
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return -EIO;
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}
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if (memc_flexspi_aps6404l_reset(dev)) {
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LOG_ERR("Could not reset pSRAM");
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return -EIO;
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}
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if (memc_flexspi_aps6404l_get_vendor_id(dev, &vendor_id)) {
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LOG_ERR("Could not read vendor id");
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return -EIO;
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}
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LOG_DBG("Vendor id: 0x%0x", vendor_id);
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if (vendor_id != APM_VENDOR_ID) {
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LOG_WRN("Vendor ID does not match expected value of 0x%0x",
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APM_VENDOR_ID);
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}
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return 0;
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}
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#define CONCAT3(x, y, z) x ## y ## z
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#define CS_INTERVAL_UNIT(unit) \
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CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
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#define AHB_WRITE_WAIT_UNIT(unit) \
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CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
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#define MEMC_FLEXSPI_DEVICE_CONFIG(n) \
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{ \
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.flexspiRootClk = DT_INST_PROP(n, spi_max_frequency), \
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.isSck2Enabled = false, \
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.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
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.addressShift = false, \
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.CSIntervalUnit = \
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CS_INTERVAL_UNIT( \
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DT_INST_PROP(n, cs_interval_unit)), \
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.CSInterval = DT_INST_PROP(n, cs_interval), \
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.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
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.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
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.dataValidTime = DT_INST_PROP(n, data_valid_time), \
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.columnspace = DT_INST_PROP(n, column_space), \
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.enableWordAddress = DT_INST_PROP(n, word_addressable), \
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.AWRSeqIndex = WRITE_DATA, \
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.AWRSeqNumber = 1, \
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.ARDSeqIndex = READ_DATA, \
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.ARDSeqNumber = 1, \
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.AHBWriteWaitUnit = \
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AHB_WRITE_WAIT_UNIT( \
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DT_INST_PROP(n, ahb_write_wait_unit)), \
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.AHBWriteWaitInterval = \
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DT_INST_PROP(n, ahb_write_wait_interval), \
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.enableWriteMask = false, \
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} \
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#define MEMC_FLEXSPI_APS6404L(n) \
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static const struct memc_flexspi_aps6404l_config \
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memc_flexspi_aps6404l_config_##n = { \
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.port = DT_INST_REG_ADDR(n), \
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.config = MEMC_FLEXSPI_DEVICE_CONFIG(n), \
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}; \
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\
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static struct memc_flexspi_aps6404l_data \
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memc_flexspi_aps6404l_data_##n = { \
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.controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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memc_flexspi_aps6404l_init, \
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NULL, \
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&memc_flexspi_aps6404l_data_##n, \
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&memc_flexspi_aps6404l_config_##n, \
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POST_KERNEL, \
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CONFIG_MEMC_INIT_PRIORITY, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(MEMC_FLEXSPI_APS6404L)
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8
dts/bindings/mtd/nxp,imx-flexspi-aps6404l.yaml
Normal file
8
dts/bindings/mtd/nxp,imx-flexspi-aps6404l.yaml
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@ -0,0 +1,8 @@
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# Copyright 2022 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: AP Memory APS6404L pSRAM on NXP FlexSPI bus
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compatible: "nxp,imx-flexspi-aps6404l"
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include: nxp,imx-flexspi-device.yaml
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