eeprom: Add Microchip eeprom driver skeleton

Prepare for Microchip eeprom driver addition. Update
dtsi, kconfig, cmake and relevant soc files for eeprom
driver addition.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>

drivers/eeprom/CMakeLists.txt

@@ -11,3 +11,4 @@ zephyr_library_sources_ifdef(CONFIG_EEPROM_STM32 eeprom_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_EEPROM_SIMULATOR eeprom_simulator.c)
 zephyr_library_sources_ifdef(CONFIG_EEPROM_EMULATOR eeprom_emulator.c)
 zephyr_library_sources_ifdef(CONFIG_EEPROM_TMP116 eeprom_tmp116.c)
+zephyr_library_sources_ifdef(CONFIG_EEPROM_XEC eeprom_mchp_xec.c)

drivers/eeprom/Kconfig

@@ -63,6 +63,7 @@ source "drivers/eeprom/Kconfig.lpc11u6x"
 source "drivers/eeprom/Kconfig.stm32"
 source "drivers/eeprom/Kconfig.eeprom_emu"
 source "drivers/eeprom/Kconfig.tmp116"
+source "drivers/eeprom/Kconfig.xec"
 
 config EEPROM_SIMULATOR
 	bool "Simulated EEPROM driver"

drivers/eeprom/Kconfig.xec

@@ -0,0 +1,11 @@
+# Microchip XEC EEPROM
+
+# Copyright (c) 2022 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config EEPROM_XEC
+	bool "MCHP XEC EEPROM driver"
+	default y
+	depends on DT_HAS_MICROCHIP_XEC_EEPROM_ENABLED
+	help
+	  Enable support for Microchip XEC EEPROM driver.

drivers/eeprom/eeprom_mchp_xec.c

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2022 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT microchip_xec_eeprom
+
+#include <zephyr/drivers/eeprom.h>
+#include <soc.h>
+
+#define LOG_LEVEL CONFIG_EEPROM_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(eeprom_xec);
+
+K_MUTEX_DEFINE(lock);
+
+struct eeprom_xec_config {
+	uint32_t addr;
+	size_t size;
+};
+
+static int eeprom_xec_read(const struct device *dev, off_t offset,
+				void *buf,
+				size_t len)
+{
+	const struct eeprom_xec_config *config = dev->config;
+
+	if (!len) {
+		return 0;
+	}
+
+	if ((offset + len) > config->size) {
+		LOG_WRN("attempt to read past device boundary");
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&lock, K_FOREVER);
+
+	/* EEPROM HW READ */
+
+	k_mutex_unlock(&lock);
+
+	return 0;
+}
+
+static int eeprom_xec_write(const struct device *dev, off_t offset,
+				const void *buf, size_t len)
+{
+	const struct eeprom_xec_config *config = dev->config;
+	int ret = 0;
+
+	if (!len) {
+		return 0;
+	}
+
+	if ((offset + len) > config->size) {
+		LOG_WRN("attempt to write past device boundary");
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&lock, K_FOREVER);
+
+	/* EEPROM HW WRITE */
+
+	k_mutex_unlock(&lock);
+
+	return ret;
+}
+
+static size_t eeprom_xec_size(const struct device *dev)
+{
+	const struct eeprom_xec_config *config = dev->config;
+
+	return config->size;
+}
+
+static int eeprom_xec_init(const struct device *dev)
+{
+	return 0;
+}
+
+static const struct eeprom_driver_api eeprom_xec_api = {
+	.read = eeprom_xec_read,
+	.write = eeprom_xec_write,
+	.size = eeprom_xec_size,
+};
+
+static const struct eeprom_xec_config eeprom_config = {
+	.addr = DT_INST_REG_ADDR(0),
+	.size = DT_INST_REG_SIZE(0),
+};
+
+DEVICE_DT_INST_DEFINE(0, &eeprom_xec_init, NULL, NULL,
+		    &eeprom_config, POST_KERNEL,
+		    CONFIG_EEPROM_INIT_PRIORITY, &eeprom_xec_api);

dts/arm/microchip/mec172x/mec172xnsz-pinctrl.dtsi

@@ -641,6 +641,24 @@
 		pinmux = < MCHP_XEC_PINMUX(076, MCHP_GPIO) >;
 	};
 
+	/* EEPROM */
+	/omit-if-no-ref/ eeprom_cs_gpio116: eeprom_cs_gpio116 {
+		pinmux = < MCHP_XEC_PINMUX(0116, MCHP_AF2) >;
+	};
+
+	/omit-if-no-ref/ eeprom_clk_gpio117: gpspi_clk_gpio117 {
+		pinmux = < MCHP_XEC_PINMUX(0117, MCHP_AF2) >;
+	};
+
+	/omit-if-no-ref/ eeprom_mosi_gpio074: eeprom_mosi_gpio074 {
+		pinmux = < MCHP_XEC_PINMUX(074, MCHP_AF2) >;
+	};
+
+	/omit-if-no-ref/ eeprom_miso_gpio075: eeprom_miso_gpio075 {
+		pinmux = < MCHP_XEC_PINMUX(075, MCHP_AF2) >;
+	};
+
+
 	/* PECI */
 	/omit-if-no-ref/ peci_dat_gpio042: peci_dat_gpio042 {
 		pinmux = < MCHP_XEC_PINMUX(042, MCHP_AF1) >;

dts/arm/microchip/mec172xnsz.dtsi

@@ -470,6 +470,15 @@
 			#dma-cells = <2>;
 			status = "disabled";
 		};
+		eeprom: eeprom@40002c00 {
+			compatible = "microchip,xec-eeprom";
+			reg = <0x40002c00 0x400>;
+			interrupts = <155 2>;
+			size = <2048>;
+			girqs = <18 13>;
+			pcrs = <4 14>;
+			status = "disabled";
+		};
 		i2c_smb_0: i2c@40004000 {
 			compatible = "microchip,xec-i2c-v2";
 			reg = <0x40004000 0x80>;

dts/bindings/mtd/microchip,xec-eeprom.yaml

@@ -0,0 +1,32 @@
+# Copyright (c) 2022 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip on-chip EEPROM
+
+compatible: "microchip,xec-eeprom"
+
+include: eeprom-base.yaml
+
+properties:
+    reg:
+      required: true
+
+    girqs:
+      type: array
+      required: true
+      description: |
+        Array of GIRQ and bit position pairs for each interrupt
+        signal the block generates.
+
+    pcrs:
+      type: array
+      required: true
+      description: PS2 PCR register index and bit position
+
+girq-cells:
+    - girqnum
+    - bitpos
+
+pcr-cells:
+    - regidx
+    - bitpos

soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnsz

@@ -23,4 +23,8 @@ config PECI_XEC
 	default y
 	depends on PECI
 
+config EEPROM_XEC
+	default y
+	depends on EEPROM
+
 endif # SOC_MEC172X_NSZ