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drivers: clock_control: stm32: enable PLL1FRACN setting

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Enables the fractional-N (FRACN) setting for PLL1 in the STM32H5XX
clock driver.
This feature allows achieving a system clock frequency of 250 MHz from
an 8 MHz `clk_hse`.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit is contained in:
Pisit Sawangvonganan 2025-01-09 02:11:08 +07:00 committed by Benjamin Cabé
parent db28dbd888
commit ce2d907e4d
1 changed files with 4 additions and 0 deletions
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4
drivers/clock_control/clock_stm32_ll_h5.c
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@ -478,6 +478,10 @@ static int set_up_plls(void)
LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
LL_RCC_PLL1FRACN_Disable();
if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {
LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE);
LL_RCC_PLL1FRACN_Enable();
}
if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);