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boards: toradex: adopt new zephyr:board directive and role

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This updates the documentation of all the Toradex boards to use
the new `zephyr:board::` directive.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit is contained in:
Benjamin Cabé 2024-10-18 16:49:35 +02:00 committed by Carles Cufí
parent 1e895fedab
commit d2072f0502
2 changed files with 2 additions and 19 deletions
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10
boards/toradex/colibri_imx7d/doc/index.rst
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@ -1,7 +1,4 @@
.. _colibri_imx7d: .. zephyr:board:: colibri_imx7d
NXP i.MX 7 Computer on Module - Colibri iMX7
############################################
Overview Overview
******** ********
@ -11,11 +8,6 @@ core and Single Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will also Zephyr was ported to run on the M4 core. In a later release, it will also
communicate with the A7 core (running Linux) via RPmsg. communicate with the A7 core (running Linux) via RPmsg.
.. image:: colibri_imx7d.jpg
:align: center
:alt: Colibri-iMX7
Hardware Hardware
******** ********

11
boards/toradex/verdin_imx8mp/doc/index.rst
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@ -1,7 +1,4 @@
.. _verdin_imx8mp: .. zephyr:board:: verdin_imx8mp
Toradex Verdin iMX8M Plus SoM
#############################
Overview Overview
******** ********
@ -34,12 +31,6 @@ Quoting NXP:
The Verdin iMX8M Plus integrates a total of 4 Arm Cortex™-A53 CPUs, operating at 1.6 GHz, alongside The Verdin iMX8M Plus integrates a total of 4 Arm Cortex™-A53 CPUs, operating at 1.6 GHz, alongside
a single Arm Cortex™-M7F microcontroller operating at 800 MHz. a single Arm Cortex™-M7F microcontroller operating at 800 MHz.
.. figure:: verdin_imx8mp_front.jpg
:align: center
:alt: Toradex Verdin iMX8M Plus
Toradex Verdin iMX8M Plus (Credit: Toradex)
Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and
energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1 energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1
memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary