drivers: serial: gecko: add new driver UART communication via EUSART
Added a new driver to support UART communication via EUSART. Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
This commit is contained in:
Yishai Jaffe
Benjamin Cabé
parent
71911eb041
commit
d5c0d7acdd
5 changed files with 562 additions and 0 deletions
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@ -72,6 +72,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_SCI_RA uart_renesas_ra_sci.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SEDI uart_sedi.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SI32_USART uart_si32_usart.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SIFIVE uart_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SILABS_EUSART uart_silabs_eusart.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SMARTBOND uart_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_UART_STELLARIS uart_stellaris.c)
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zephyr_library_sources_ifdef(CONFIG_UART_STM32 uart_stm32.c)
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@ -214,6 +214,7 @@ rsource "Kconfig.rzt2m"
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rsource "Kconfig.sam0"
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rsource "Kconfig.sedi"
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rsource "Kconfig.sifive"
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rsource "Kconfig.silabs_eusart"
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rsource "Kconfig.smartbond"
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rsource "Kconfig.stellaris"
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rsource "Kconfig.stm32"
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15
drivers/serial/Kconfig.silabs_eusart
Normal file
15
drivers/serial/Kconfig.silabs_eusart
Normal file
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@ -0,0 +1,15 @@
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# Copyright (c) 2024, Yishai Jaffe
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# SPDX-License-Identifier: Apache-2.0
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config UART_SILABS_EUSART
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bool "Silabs EUSART UART driver"
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default y
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depends on DT_HAS_SILABS_EUSART_UART_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select SOC_GECKO_EUSART
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select PINCTRL
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select CLOCK_CONTROL
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select PM_DEVICE if PM
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help
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Enable the eusart uart driver.
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518
drivers/serial/uart_silabs_eusart.c
Normal file
518
drivers/serial/uart_silabs_eusart.c
Normal file
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@ -0,0 +1,518 @@
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/*
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* Copyright (c) 2024, Yishai Jaffe
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT silabs_eusart_uart
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#include <errno.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/clock_control_silabs.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/irq.h>
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#include <zephyr/pm/device.h>
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#include <em_eusart.h>
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struct uart_silabs_eusart_config {
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EUSART_TypeDef *eusart;
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const struct pinctrl_dev_config *pcfg;
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const struct device *clock_dev;
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const struct silabs_clock_control_cmu_config clock_cfg;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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void (*irq_config_func)(const struct device *dev);
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#endif
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};
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struct uart_silabs_eusart_data {
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struct uart_config uart_cfg;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t callback;
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void *cb_data;
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#endif
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};
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static int uart_silabs_eusart_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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if (EUSART_StatusGet(config->eusart) & EUSART_STATUS_RXFL) {
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*c = EUSART_Rx(config->eusart);
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return 0;
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}
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return -1;
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}
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static void uart_silabs_eusart_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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/* EUSART_Tx function already waits for the transmit buffer being empty
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* and waits for the bus to be free to transmit.
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*/
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EUSART_Tx(config->eusart, c);
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}
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static int uart_silabs_eusart_err_check(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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uint32_t flags = EUSART_IntGet(config->eusart);
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int err = 0;
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if (flags & EUSART_IF_RXOF) {
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err |= UART_ERROR_OVERRUN;
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}
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if (flags & EUSART_IF_PERR) {
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err |= UART_ERROR_PARITY;
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}
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if (flags & EUSART_IF_FERR) {
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err |= UART_ERROR_FRAMING;
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}
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EUSART_IntClear(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
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return err;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_silabs_eusart_fifo_fill(const struct device *dev,
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const uint8_t *tx_data,
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int len)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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int num_tx = 0;
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while ((len - num_tx > 0) &&
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(EUSART_StatusGet(config->eusart) & EUSART_STATUS_TXFL)) {
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config->eusart->TXDATA = (uint32_t)tx_data[num_tx++];
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}
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if (!(EUSART_StatusGet(config->eusart) & EUSART_STATUS_TXFL)) {
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EUSART_IntClear(config->eusart, EUSART_IF_TXFL);
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}
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return num_tx;
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}
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static int uart_silabs_eusart_fifo_read(const struct device *dev, uint8_t *rx_data,
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const int len)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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int num_rx = 0;
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while ((len - num_rx > 0) &&
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(EUSART_StatusGet(config->eusart) & EUSART_STATUS_RXFL)) {
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rx_data[num_rx++] = (uint8_t)config->eusart->RXDATA;
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}
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if (!(EUSART_StatusGet(config->eusart) & EUSART_STATUS_RXFL)) {
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EUSART_IntClear(config->eusart, EUSART_IF_RXFL);
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}
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return num_rx;
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}
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static void uart_silabs_eusart_irq_tx_enable(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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EUSART_IntClear(config->eusart, EUSART_IEN_TXFL | EUSART_IEN_TXC);
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EUSART_IntEnable(config->eusart, EUSART_IEN_TXFL | EUSART_IEN_TXC);
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}
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static void uart_silabs_eusart_irq_tx_disable(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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EUSART_IntDisable(config->eusart, EUSART_IEN_TXFL | EUSART_IEN_TXC);
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EUSART_IntClear(config->eusart, EUSART_IEN_TXFL | EUSART_IEN_TXC);
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}
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static int uart_silabs_eusart_irq_tx_complete(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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uint32_t flags = EUSART_IntGet(config->eusart);
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EUSART_IntClear(config->eusart, EUSART_IF_TXC);
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return (flags & EUSART_IF_TXC) != 0;
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}
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static int uart_silabs_eusart_irq_tx_ready(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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return (config->eusart->IEN & EUSART_IEN_TXFL)
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&& (EUSART_IntGet(config->eusart) & EUSART_IF_TXFL);
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}
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static void uart_silabs_eusart_irq_rx_enable(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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EUSART_IntClear(config->eusart, EUSART_IEN_RXFL);
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EUSART_IntEnable(config->eusart, EUSART_IEN_RXFL);
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}
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static void uart_silabs_eusart_irq_rx_disable(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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EUSART_IntDisable(config->eusart, EUSART_IEN_RXFL);
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EUSART_IntClear(config->eusart, EUSART_IEN_RXFL);
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}
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static int uart_silabs_eusart_irq_rx_ready(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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return (config->eusart->IEN & EUSART_IEN_RXFL)
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&& (EUSART_IntGet(config->eusart) & EUSART_IF_RXFL);
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}
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static void uart_silabs_eusart_irq_err_enable(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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EUSART_IntClear(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
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EUSART_IntEnable(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
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}
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static void uart_silabs_eusart_irq_err_disable(const struct device *dev)
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{
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const struct uart_silabs_eusart_config *config = dev->config;
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EUSART_IntDisable(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
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EUSART_IntClear(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
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}
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static int uart_silabs_eusart_irq_is_pending(const struct device *dev)
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{
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return uart_silabs_eusart_irq_tx_ready(dev) || uart_silabs_eusart_irq_rx_ready(dev);
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}
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static int uart_silabs_eusart_irq_update(const struct device *dev)
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{
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return 1;
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}
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static void uart_silabs_eusart_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct uart_silabs_eusart_data *data = dev->data;
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data->callback = cb;
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data->cb_data = cb_data;
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}
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static void uart_silabs_eusart_isr(const struct device *dev)
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{
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struct uart_silabs_eusart_data *data = dev->data;
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if (data->callback) {
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data->callback(dev, data->cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static inline EUSART_Parity_TypeDef uart_silabs_eusart_cfg2ll_parity(
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enum uart_config_parity parity)
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{
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switch (parity) {
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case UART_CFG_PARITY_ODD:
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return eusartOddParity;
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case UART_CFG_PARITY_EVEN:
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return eusartEvenParity;
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case UART_CFG_PARITY_NONE:
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default:
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return eusartNoParity;
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}
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}
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static inline enum uart_config_parity uart_silabs_eusart_ll2cfg_parity(
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EUSART_Parity_TypeDef parity)
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{
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switch (parity) {
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case eusartOddParity:
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return UART_CFG_PARITY_ODD;
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case eusartEvenParity:
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return UART_CFG_PARITY_EVEN;
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case eusartNoParity:
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default:
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return UART_CFG_PARITY_NONE;
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}
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}
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static inline EUSART_Stopbits_TypeDef uart_silabs_eusart_cfg2ll_stopbits(
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enum uart_config_stop_bits sb)
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{
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switch (sb) {
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case UART_CFG_STOP_BITS_0_5:
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return eusartStopbits0p5;
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case UART_CFG_STOP_BITS_1:
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return eusartStopbits1;
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case UART_CFG_STOP_BITS_2:
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return eusartStopbits2;
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case UART_CFG_STOP_BITS_1_5:
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return eusartStopbits1p5;
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default:
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return eusartStopbits1;
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}
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}
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static inline enum uart_config_stop_bits uart_silabs_eusart_ll2cfg_stopbits(
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EUSART_Stopbits_TypeDef sb)
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{
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switch (sb) {
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case eusartStopbits0p5:
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return UART_CFG_STOP_BITS_0_5;
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case eusartStopbits1:
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return UART_CFG_STOP_BITS_1;
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case eusartStopbits1p5:
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return UART_CFG_STOP_BITS_1_5;
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case eusartStopbits2:
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return UART_CFG_STOP_BITS_2;
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default:
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return UART_CFG_STOP_BITS_1;
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}
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}
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static inline EUSART_Databits_TypeDef uart_silabs_eusart_cfg2ll_databits(
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enum uart_config_data_bits db, enum uart_config_parity p)
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{
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switch (db) {
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case UART_CFG_DATA_BITS_7:
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if (p == UART_CFG_PARITY_NONE) {
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return eusartDataBits7;
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} else {
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return eusartDataBits8;
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}
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case UART_CFG_DATA_BITS_9:
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return eusartDataBits9;
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case UART_CFG_DATA_BITS_8:
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default:
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if (p == UART_CFG_PARITY_NONE) {
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return eusartDataBits8;
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} else {
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return eusartDataBits9;
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}
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return eusartDataBits8;
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}
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}
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static inline enum uart_config_data_bits uart_silabs_eusart_ll2cfg_databits(
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EUSART_Databits_TypeDef db, EUSART_Parity_TypeDef p)
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{
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switch (db) {
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case eusartDataBits7:
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if (p == eusartNoParity) {
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return UART_CFG_DATA_BITS_7;
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} else {
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return UART_CFG_DATA_BITS_6;
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}
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case eusartDataBits9:
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if (p == eusartNoParity) {
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return UART_CFG_DATA_BITS_9;
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} else {
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return UART_CFG_DATA_BITS_8;
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}
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case eusartDataBits8:
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default:
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if (p == eusartNoParity) {
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return UART_CFG_DATA_BITS_8;
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} else {
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return UART_CFG_DATA_BITS_7;
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}
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}
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}
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/**
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* @brief Get LL hardware flow control define from
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* Zephyr hardware flow control option.
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* @note Supports only UART_CFG_FLOW_CTRL_RTS_CTS and UART_CFG_FLOW_CTRL_RS485.
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* @param fc: Zephyr hardware flow control option.
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* @retval eusartHwFlowControlCtsAndRts, or eusartHwFlowControlNone.
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*/
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static inline EUSART_HwFlowControl_TypeDef uart_silabs_eusart_cfg2ll_hwctrl(
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enum uart_config_flow_control fc)
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{
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if (fc == UART_CFG_FLOW_CTRL_RTS_CTS) {
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return eusartHwFlowControlCtsAndRts;
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}
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return eusartHwFlowControlNone;
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}
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/**
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* @brief Get Zephyr hardware flow control option from
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* LL hardware flow control define.
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* @note Supports only eusartHwFlowControlCtsAndRts.
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* @param fc: LL hardware flow control definition.
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* @retval UART_CFG_FLOW_CTRL_RTS_CTS, or UART_CFG_FLOW_CTRL_NONE.
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*/
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static inline enum uart_config_flow_control uart_silabs_eusart_ll2cfg_hwctrl(
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EUSART_HwFlowControl_TypeDef fc)
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{
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if (fc == eusartHwFlowControlCtsAndRts) {
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return UART_CFG_FLOW_CTRL_RTS_CTS;
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}
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return UART_CFG_FLOW_CTRL_NONE;
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}
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/**
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* @brief Main initializer for UART
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*
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* @param dev UART device to be initialized
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* @return int 0
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*/
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static int uart_silabs_eusart_init(const struct device *dev)
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{
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int err;
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const struct uart_silabs_eusart_config *config = dev->config;
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struct uart_silabs_eusart_data *data = dev->data;
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struct uart_config *uart_cfg = &data->uart_cfg;
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EUSART_UartInit_TypeDef eusartInit = EUSART_UART_INIT_DEFAULT_HF;
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EUSART_AdvancedInit_TypeDef advancedSettings = EUSART_ADVANCED_INIT_DEFAULT;
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/* The peripheral and gpio clock are already enabled from soc and gpio
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* driver
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*/
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/* Enable EUSART clock */
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err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg);
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if (err < 0) {
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return err;
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}
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err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (err < 0) {
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||||
return err;
|
||||
}
|
||||
|
||||
/* Init EUSART */
|
||||
eusartInit.baudrate = uart_cfg->baudrate;
|
||||
eusartInit.parity = uart_silabs_eusart_cfg2ll_parity(uart_cfg->parity);
|
||||
eusartInit.stopbits = uart_silabs_eusart_cfg2ll_stopbits(uart_cfg->stop_bits);
|
||||
eusartInit.databits = uart_silabs_eusart_cfg2ll_databits(uart_cfg->data_bits,
|
||||
uart_cfg->parity);
|
||||
advancedSettings.hwFlowControl = uart_silabs_eusart_cfg2ll_hwctrl(uart_cfg->flow_ctrl);
|
||||
eusartInit.advancedSettings = &advancedSettings;
|
||||
|
||||
EUSART_UartInitHf(config->eusart, &eusartInit);
|
||||
|
||||
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
||||
config->irq_config_func(dev);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_DEVICE
|
||||
static int uart_silabs_eusart_pm_action(const struct device *dev, enum pm_device_action action)
|
||||
{
|
||||
__maybe_unused const struct uart_silabs_eusart_config *config = dev->config;
|
||||
|
||||
switch (action) {
|
||||
case PM_DEVICE_ACTION_SUSPEND:
|
||||
#ifdef EUSART_STATUS_TXIDLE
|
||||
/* Wait for TX FIFO to flush before suspending */
|
||||
while (!(EUSART_StatusGet(config->eusart) & EUSART_STATUS_TXIDLE)) {
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
|
||||
case PM_DEVICE_ACTION_RESUME:
|
||||
break;
|
||||
|
||||
default:
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static DEVICE_API(uart, uart_silabs_eusart_driver_api) = {
|
||||
.poll_in = uart_silabs_eusart_poll_in,
|
||||
.poll_out = uart_silabs_eusart_poll_out,
|
||||
.err_check = uart_silabs_eusart_err_check,
|
||||
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
||||
.fifo_fill = uart_silabs_eusart_fifo_fill,
|
||||
.fifo_read = uart_silabs_eusart_fifo_read,
|
||||
.irq_tx_enable = uart_silabs_eusart_irq_tx_enable,
|
||||
.irq_tx_disable = uart_silabs_eusart_irq_tx_disable,
|
||||
.irq_tx_complete = uart_silabs_eusart_irq_tx_complete,
|
||||
.irq_tx_ready = uart_silabs_eusart_irq_tx_ready,
|
||||
.irq_rx_enable = uart_silabs_eusart_irq_rx_enable,
|
||||
.irq_rx_disable = uart_silabs_eusart_irq_rx_disable,
|
||||
.irq_rx_ready = uart_silabs_eusart_irq_rx_ready,
|
||||
.irq_err_enable = uart_silabs_eusart_irq_err_enable,
|
||||
.irq_err_disable = uart_silabs_eusart_irq_err_disable,
|
||||
.irq_is_pending = uart_silabs_eusart_irq_is_pending,
|
||||
.irq_update = uart_silabs_eusart_irq_update,
|
||||
.irq_callback_set = uart_silabs_eusart_irq_callback_set,
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
||||
#define UART_IRQ_HANDLER_FUNC(idx) \
|
||||
.irq_config_func = uart_silabs_eusart_config_func_##idx,
|
||||
#define UART_IRQ_HANDLER(idx) \
|
||||
static void uart_silabs_eusart_config_func_##idx(const struct device *dev) \
|
||||
{ \
|
||||
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, rx, irq), \
|
||||
DT_INST_IRQ_BY_NAME(idx, rx, priority), \
|
||||
uart_silabs_eusart_isr, DEVICE_DT_INST_GET(idx), 0); \
|
||||
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, tx, irq), \
|
||||
DT_INST_IRQ_BY_NAME(idx, tx, priority), \
|
||||
uart_silabs_eusart_isr, DEVICE_DT_INST_GET(idx), 0); \
|
||||
\
|
||||
irq_enable(DT_INST_IRQ_BY_NAME(idx, rx, irq)); \
|
||||
irq_enable(DT_INST_IRQ_BY_NAME(idx, tx, irq)); \
|
||||
}
|
||||
#else
|
||||
#define UART_IRQ_HANDLER_FUNC(idx)
|
||||
#define UART_IRQ_HANDLER(idx)
|
||||
#endif
|
||||
|
||||
#define UART_INIT(idx) \
|
||||
UART_IRQ_HANDLER(idx) \
|
||||
\
|
||||
PINCTRL_DT_INST_DEFINE(idx); \
|
||||
\
|
||||
static const struct uart_silabs_eusart_config uart_silabs_eusart_cfg_##idx = { \
|
||||
.eusart = (EUSART_TypeDef *)DT_INST_REG_ADDR(idx), \
|
||||
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
|
||||
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
|
||||
.clock_cfg = SILABS_DT_INST_CLOCK_CFG(idx), \
|
||||
UART_IRQ_HANDLER_FUNC(idx) \
|
||||
}; \
|
||||
\
|
||||
static struct uart_silabs_eusart_data uart_silabs_eusart_data_##idx = { \
|
||||
.uart_cfg = { \
|
||||
.baudrate = DT_INST_PROP(idx, current_speed), \
|
||||
.parity = DT_INST_ENUM_IDX(idx, parity), \
|
||||
.stop_bits = DT_INST_ENUM_IDX(idx, stop_bits), \
|
||||
.data_bits = DT_INST_ENUM_IDX(idx, data_bits), \
|
||||
.flow_ctrl = DT_INST_PROP(idx, hw_flow_control) \
|
||||
? UART_CFG_FLOW_CTRL_RTS_CTS \
|
||||
: UART_CFG_FLOW_CTRL_NONE, \
|
||||
}, \
|
||||
}; \
|
||||
\
|
||||
PM_DEVICE_DT_INST_DEFINE(idx, uart_silabs_eusart_pm_action); \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(idx, uart_silabs_eusart_init, PM_DEVICE_DT_INST_GET(idx), \
|
||||
&uart_silabs_eusart_data_##idx, \
|
||||
&uart_silabs_eusart_cfg_##idx, PRE_KERNEL_1, \
|
||||
CONFIG_SERIAL_INIT_PRIORITY, \
|
||||
&uart_silabs_eusart_driver_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(UART_INIT)
|
||||
27
dts/bindings/serial/silabs,eusart-uart.yaml
Normal file
27
dts/bindings/serial/silabs,eusart-uart.yaml
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
description: Silabs EUSART UART
|
||||
|
||||
compatible: "silabs,eusart-uart"
|
||||
|
||||
include: [uart-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
current-speed:
|
||||
description: |
|
||||
Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
|
||||
default: 115200
|
||||
|
||||
stop-bits:
|
||||
description: |
|
||||
Sets the number of stop bits. Defaults to standard of 1 if not specified.
|
||||
default: "1"
|
||||
|
||||
data-bits:
|
||||
description: |
|
||||
Sets the number of data bits. Defaults to standard of 8 if not specified.
|
||||
default: 8
|
||||
Loading…
Reference in a new issue