adafruit-mirror/zephyr
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 8

adsp: boot: power: Separate watchdog state from core power

Browse source 
The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This commit is contained in:
Adrian Warecki 2023-01-09 14:55:05 +01:00 committed by Anas Nashif
parent da4f20901f
commit ddad6226c0
3 changed files with 0 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h
View file

@ -57,9 +57,6 @@ struct dspcs {
#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15)
#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16)
#define DSPBR_WDT_RESUME BIT(8)
#define DSPBR_WDT_RESTART_COMMAND 0x76
#define DSPCS (*(volatile struct dspcs *)DSPCS_REG)
#endif /* ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ */

5
soc/xtensa/intel_adsp/ace/multiprocessing.c
View file

@ -129,11 +129,6 @@ void soc_mp_startup(uint32_t cpu)
/* Prevent idle from powering us off */
DSPCS.bootctl[cpu].bctl |=
DSPBR_BCTL_WAITIPCG | DSPBR_BCTL_WAITIPPG;
/* checking if WDT was stopped during D3 transition */
if (DSPCS.bootctl[cpu].wdtcs & DSPBR_WDT_RESUME) {
DSPCS.bootctl[cpu].wdtcs = DSPBR_WDT_RESUME;
/* TODO: delete this IF when FW starts using imr restore vector */
}
}
void arch_sched_ipi(void)

2
soc/xtensa/intel_adsp/ace/power.c
View file

@ -221,7 +221,6 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
core_desc[cpu].intenable = XTENSA_RSR("INTENABLE");
z_xt_ints_off(0xffffffff);
core_desc[cpu].bctl = DSPCS.bootctl[cpu].bctl;
DSPCS.bootctl[cpu].wdtcs = DSPBR_WDT_RESTART_COMMAND;
DSPCS.bootctl[cpu].bctl &= ~DSPBR_BCTL_WAITIPCG;
soc_cpus_active[cpu] = false;
z_xtensa_cache_flush_inv_all();
@ -309,7 +308,6 @@ __weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
uint32_t cpu = arch_proc_id();
if (state == PM_STATE_SOFT_OFF) {
DSPCS.bootctl[cpu].wdtcs = DSPBR_WDT_RESUME;
/* restore clock gating state */
DSPCS.bootctl[cpu].bctl |=
(core_desc[0].bctl & DSPBR_BCTL_WAITIPCG);