drivers: flash: stm32: add STM32WB0 flash controller
Adds a basic driver for the STM32WB0 flash controller (read/erase/write). Extended operations are not supported by this driver. Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This commit is contained in:
Mathieu Choplain
Carles Cufí
parent
263b03feeb
commit
e322fa9781
2 changed files with 461 additions and 0 deletions
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@ -84,6 +84,8 @@ if(CONFIG_SOC_FLASH_STM32)
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else()
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zephyr_library_sources_ifdef(CONFIG_DT_HAS_ST_STM32_FLASH_CONTROLLER_ENABLED flash_stm32.c flash_stm32wbax.c)
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endif()
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elseif(CONFIG_SOC_SERIES_STM32WB0X)
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zephyr_library_sources_ifdef(CONFIG_DT_HAS_ST_STM32WB0_FLASH_CONTROLLER_ENABLED flash_stm32wb0x.c)
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else()
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if(CONFIG_DT_HAS_ST_STM32_FLASH_CONTROLLER_ENABLED)
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zephyr_library_sources(flash_stm32.c)
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459
drivers/flash/flash_stm32wb0x.c
Normal file
459
drivers/flash/flash_stm32wb0x.c
Normal file
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@ -0,0 +1,459 @@
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32wb0_flash_controller
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/flash.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/sys/math_extras.h>
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/* <soc.h> also brings "stm32wb0x_hal_flash.h"
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* and "system_stm32wb0x.h", which provide macros
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* used by the driver, such as FLASH_PAGE_SIZE or
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* _MEMORY_FLASH_SIZE_ respectively.
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_system.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(flash_stm32wb0x, CONFIG_FLASH_LOG_LEVEL);
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/**
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* Driver private definitions & assertions
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*/
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#define SYSTEM_FLASH_SIZE _MEMORY_FLASH_SIZE_
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#define PAGES_IN_FLASH (SYSTEM_FLASH_SIZE / FLASH_PAGE_SIZE)
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#define WRITE_BLOCK_SIZE \
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DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
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/* Size of flash words, in bytes (equal to write block size) */
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#define WORD_SIZE WRITE_BLOCK_SIZE
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#define ERASE_BLOCK_SIZE \
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DT_PROP(DT_INST(0, soc_nv_flash), erase_block_size)
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/**
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* Driver private structures
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*/
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struct flash_wb0x_data {
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/** Used to serialize write/erase operations */
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struct k_sem write_lock;
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/** Flash size, in bytes */
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size_t flash_size;
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};
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/**
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* Driver private utility functions
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*/
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static inline uint32_t read_mem_u32(const uint32_t *ptr)
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{
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/**
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* Fetch word using sys_get_le32, which performs byte-sized
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* reads instead of word-sized. This is important as ptr may
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* be unaligned. We also want to use le32 because the data is
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* stored in little-endian inside the flash.
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*/
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return sys_get_le32((const uint8_t *)ptr);
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}
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static inline size_t get_flash_size_in_bytes(void)
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{
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/* FLASH.SIZE contains the highest flash address supported
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* on this MCU, which is also the number of words in flash
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* minus one.
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*/
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const uint32_t words_in_flash =
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READ_BIT(FLASH->SIZE, FLASH_FLASH_SIZE_FLASH_SIZE) + 1;
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return words_in_flash * WORD_SIZE;
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}
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/**
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* @brief Returns the associated error to IRQ flags.
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*
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* @returns a negative error value
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*/
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static int error_from_irq_flags(uint32_t flags)
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{
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/**
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* Only two errors are expected:
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* - illegal command
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* - command error
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*/
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if (flags & FLASH_FLAG_ILLCMD) {
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return -EINVAL;
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}
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if (flags & FLASH_FLAG_CMDERR) {
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return -EIO;
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}
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/*
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* Unexpected error flag -> "out of domain"
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* In practice, this should never be reached.
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*/
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return -EDOM;
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}
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static bool is_valid_flash_range(const struct device *dev,
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off_t offset, uint32_t len)
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{
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const struct flash_wb0x_data *data = dev->data;
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uint32_t offset_plus_len;
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/* (offset + len) must not overflow */
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return !u32_add_overflow(offset, len, &offset_plus_len)
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/* offset must be a valid offset in flash */
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&& IN_RANGE(offset, 0, data->flash_size - 1)
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/* (offset + len) must be in [0; flash size]
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* because it is equal to the last accessed
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* byte in flash plus one (an access of `len`
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* bytes starting at `offset` touches bytes
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* `offset` to `offset + len` EXCLUDED)
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*/
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&& IN_RANGE(offset_plus_len, 0, data->flash_size);
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}
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static bool is_writeable_flash_range(const struct device *dev,
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off_t offset, uint32_t len)
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{
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if ((offset % WRITE_BLOCK_SIZE) != 0
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|| (len % WRITE_BLOCK_SIZE) != 0) {
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return false;
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}
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return is_valid_flash_range(dev, offset, len);
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}
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static bool is_erasable_flash_range(const struct device *dev,
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off_t offset, uint32_t len)
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{
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if ((offset % ERASE_BLOCK_SIZE) != 0
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|| (len % ERASE_BLOCK_SIZE) != 0) {
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return false;
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}
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return is_valid_flash_range(dev, offset, len);
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}
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/**
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* Driver private functions
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*/
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static uint32_t poll_flash_controller(void)
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{
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uint32_t flags;
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/* Poll until an interrupt flag is raised */
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do {
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flags = FLASH->IRQRAW;
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} while (flags == 0);
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/* Acknowledge the flag(s) we have seen */
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FLASH->IRQRAW = flags;
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return flags;
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}
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static int execute_flash_command(uint8_t cmd)
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{
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uint32_t irq_flags;
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/* Clear all pending interrupt bits */
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FLASH->IRQRAW = FLASH->IRQRAW;
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/* Start command */
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FLASH->COMMAND = cmd;
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/* Wait for CMDSTART */
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irq_flags = poll_flash_controller();
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/* If command didn't start, an error occurred */
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if (!(irq_flags & FLASH_IT_CMDSTART)) {
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return error_from_irq_flags(irq_flags);
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}
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/**
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* Both CMDSTART and CMDDONE may be set if the command was
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* executed fast enough. In this case, we're already done.
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* Otherwise, we need to poll again until CMDDONE/error occurs.
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*/
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if (!(irq_flags & FLASH_IT_CMDDONE)) {
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irq_flags = poll_flash_controller();
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}
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if (!(irq_flags & FLASH_IT_CMDDONE)) {
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return error_from_irq_flags(irq_flags);
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} else {
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return 0;
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}
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}
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int erase_page_range(uint32_t start_page, uint32_t page_count)
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{
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int res = 0;
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__ASSERT_NO_MSG(start_page < PAGES_IN_FLASH);
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__ASSERT_NO_MSG((start_page + page_count - 1) < PAGES_IN_FLASH);
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for (uint32_t i = start_page;
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i < (start_page + page_count);
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i++) {
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/* ADDRESS[16:9] = XADR[10:3] (address of page to erase)
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* ADDRESS[8:0] = 0 (row & word address, must be 0)
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*/
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FLASH->ADDRESS = (i << 9);
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res = execute_flash_command(FLASH_CMD_ERASE_PAGES);
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if (res < 0) {
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break;
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}
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}
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return res;
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}
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int write_word_range(const void *buf, uint32_t start_word, uint32_t num_words)
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{
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/* Special value to load in DATAx registers to skip
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* writing corresponding word with BURSTWRITE command.
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*/
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const uint32_t BURST_IGNORE_VALUE = 0xFFFFFFFF;
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const size_t WORDS_IN_BURST = 4;
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uint32_t dst_addr = start_word;
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uint32_t remaining = num_words;
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/**
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* Note that @p buf may not be aligned to 32-bit boundary.
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* However, declaring src_ptr as uint32_t* makes the address
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* increment by 4 every time we do src_ptr++, which makes it
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* behave like the other counters in this function.
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*/
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const uint32_t *src_ptr = buf;
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int res = 0;
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/**
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* Write to flash is performed as a 3 step process:
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* - write single words using WRITE commands until the write
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* write address is aligned to flash quadword boundary
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*
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* - after write address is aligned to quadword, we can use
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* the BURSTWRITE commands to write 4 words at a time
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*
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* - once less than 4 words remain to write, a last BURSTWRITE
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* is used with unneeded DATAx registers filled with 0xFFFFFFFF
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* (this makes BURSTWRITE ignore write to these addresses)
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*/
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/* (1) Align to quadword boundary with WRITE commands */
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while (remaining > 0 && (dst_addr % WORDS_IN_BURST) != 0) {
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FLASH->ADDRESS = dst_addr;
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FLASH->DATA0 = read_mem_u32(src_ptr);
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res = execute_flash_command(FLASH_CMD_WRITE);
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if (res < 0) {
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return res;
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}
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src_ptr++;
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dst_addr++;
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remaining--;
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}
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/* (2) Write bursts of quadwords */
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while (remaining >= WORDS_IN_BURST) {
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__ASSERT_NO_MSG((dst_addr % WORDS_IN_BURST) == 0);
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FLASH->ADDRESS = dst_addr;
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FLASH->DATA0 = read_mem_u32(src_ptr + 0);
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FLASH->DATA1 = read_mem_u32(src_ptr + 1);
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FLASH->DATA2 = read_mem_u32(src_ptr + 2);
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FLASH->DATA3 = read_mem_u32(src_ptr + 3);
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res = execute_flash_command(FLASH_CMD_BURSTWRITE);
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if (res < 0) {
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return res;
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}
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src_ptr += WORDS_IN_BURST;
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dst_addr += WORDS_IN_BURST;
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remaining -= WORDS_IN_BURST;
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}
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/* (3) Write trailing (between 1 and 3 words) */
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if (remaining > 0) {
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__ASSERT_NO_MSG(remaining < WORDS_IN_BURST);
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__ASSERT_NO_MSG((dst_addr % WORDS_IN_BURST) == 0);
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FLASH->ADDRESS = dst_addr;
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FLASH->DATA0 = read_mem_u32(src_ptr + 0);
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FLASH->DATA1 = (remaining >= 2)
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? read_mem_u32(src_ptr + 1)
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: BURST_IGNORE_VALUE;
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FLASH->DATA2 = (remaining == 3)
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? read_mem_u32(src_ptr + 2)
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: BURST_IGNORE_VALUE;
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FLASH->DATA3 = BURST_IGNORE_VALUE;
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remaining = 0;
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res = execute_flash_command(FLASH_CMD_BURSTWRITE);
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}
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return res;
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}
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/**
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* Driver subsystem API implementation
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*/
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int flash_wb0x_read(const struct device *dev, off_t offset,
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void *buffer, size_t len)
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{
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if (!len) {
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return 0;
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}
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if (!is_valid_flash_range(dev, offset, len)) {
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return -EINVAL;
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}
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const uint8_t *flash_base = ((void *)DT_REG_ADDR(DT_INST(0, st_stm32_nv_flash)));
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memcpy(buffer, flash_base + (uint32_t)offset, len);
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return 0;
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}
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int flash_wb0x_write(const struct device *dev, off_t offset,
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const void *buffer, size_t len)
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{
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struct flash_wb0x_data *data = dev->data;
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int res;
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if (!len) {
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return 0;
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}
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if (!is_writeable_flash_range(dev, offset, len)) {
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return -EINVAL;
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}
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/* Acquire driver lock */
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res = k_sem_take(&data->write_lock, K_NO_WAIT);
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if (res < 0) {
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return res;
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}
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const uint32_t start_word = (uint32_t)offset / WORD_SIZE;
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const uint32_t num_words = len / WORD_SIZE;
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res = write_word_range(buffer, start_word, num_words);
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/* Release driver lock */
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k_sem_give(&data->write_lock);
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return res;
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}
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int flash_wb0x_erase(const struct device *dev, off_t offset, size_t size)
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{
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struct flash_wb0x_data *data = dev->data;
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int res;
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if (!size) {
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return 0;
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}
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if (!is_erasable_flash_range(dev, offset, size)) {
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return -EINVAL;
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}
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/* Acquire driver lock */
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res = k_sem_take(&data->write_lock, K_NO_WAIT);
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if (res < 0) {
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return res;
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}
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const uint32_t start_page = (uint32_t)offset / ERASE_BLOCK_SIZE;
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const uint32_t page_count = size / ERASE_BLOCK_SIZE;
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res = erase_page_range(start_page, page_count);
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/* Release driver lock */
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k_sem_give(&data->write_lock);
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return res;
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}
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const struct flash_parameters *flash_wb0x_get_parameters(
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const struct device *dev)
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{
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static const struct flash_parameters fp = {
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.write_block_size = WRITE_BLOCK_SIZE,
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.erase_value = 0xff,
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};
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return &fp;
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}
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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void flash_wb0x_pages_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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/**
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* STM32WB0 flash: single bank, 2KiB pages
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* (the number of pages depends on MCU)
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*/
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static const struct flash_pages_layout fpl[] = {{
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.pages_count = PAGES_IN_FLASH,
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.pages_size = FLASH_PAGE_SIZE
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}};
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*layout = fpl;
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*layout_size = ARRAY_SIZE(fpl);
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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static const struct flash_driver_api flash_wb0x_api = {
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.erase = flash_wb0x_erase,
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.write = flash_wb0x_write,
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.read = flash_wb0x_read,
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.get_parameters = flash_wb0x_get_parameters,
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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.page_layout = flash_wb0x_pages_layout,
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#endif
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/* extended operations not supported */
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};
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int stm32wb0x_flash_init(const struct device *dev)
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{
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struct flash_wb0x_data *data = dev->data;
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k_sem_init(&data->write_lock, 1, 1);
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data->flash_size = get_flash_size_in_bytes();
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return 0;
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}
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/**
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* Driver device instantiation
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*/
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static struct flash_wb0x_data wb0x_flash_drv_data;
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DEVICE_DT_INST_DEFINE(0, stm32wb0x_flash_init, NULL,
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&wb0x_flash_drv_data, NULL, POST_KERNEL,
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CONFIG_FLASH_INIT_PRIORITY, &flash_wb0x_api);
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