arch: port nocache linker code to use Cmake function

Remove from linker.ld

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>

arch/common/CMakeLists.txt

@@ -20,3 +20,8 @@ zephyr_linker_sources_ifdef(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
   RAM_SECTIONS
   ramfunc.ld
 )
+
+zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
+  RAM_SECTIONS
+  nocache.ld
+)

arch/common/nocache.ld

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ * Copyright (c) 2019 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Copied from linker.ld */
+
+/* Non-cached region of RAM */
+SECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
+{
+	MPU_ALIGN(_nocache_ram_size);
+	_nocache_ram_start = .;
+	*(.nocache)
+	*(".nocache.*")
+	MPU_ALIGN(_nocache_ram_size);
+	_nocache_ram_end = .;
+} GROUP_LINK_IN(RAMABLE_REGION)
+_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;

include/arch/arm/cortex_m/scripts/linker.ld

@@ -361,20 +361,6 @@ SECTIONS
 
 #endif /* CONFIG_COVERAGE_GCOV */
 
-#if defined(CONFIG_NOCACHE_MEMORY)
-	/* Non-cached region of RAM */
-	SECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
-	{
-		MPU_ALIGN(_nocache_ram_size);
-		_nocache_ram_start = .;
-		*(.nocache)
-		*(".nocache.*")
-		MPU_ALIGN(_nocache_ram_size);
-		_nocache_ram_end = .;
-	} GROUP_LINK_IN(RAMABLE_REGION)
-	_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;
-#endif /* CONFIG_NOCACHE_MEMORY */
-
 /* Located in generated directory. This file is populated by the
  * zephyr_linker_sources() Cmake function.
  */