dts: riscv: add DTS and related bindings of andes_ae350 soc
Add DTSI file of andes_ae350 SoC and bindings of GPIO driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
This commit is contained in:
Jim Shu
Anas Nashif
parent
d7b53226d1
commit
e4cb3469d6
2 changed files with 309 additions and 0 deletions
27
dts/bindings/gpio/andestech,atcgpio100.yaml
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27
dts/bindings/gpio/andestech,atcgpio100.yaml
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# Copyright (c) 2021, Andes Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description:
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This is a representation of Andes Technology atcgpio100 GPIO node
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compatible: "andestech,atcgpio100"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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label:
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required: true
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interrupts:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags
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282
dts/riscv/andes_v5_ae350.dtsi
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282
dts/riscv/andes_v5_ae350.dtsi
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/*
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* Copyright (c) 2021 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <mem.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <60000000>;
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CPU0: cpu@0 {
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compatible = "riscv";
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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riscv,isa = "rv32imafdcxandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU1: cpu@1 {
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compatible = "riscv";
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device_type = "cpu";
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reg = <1>;
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status = "okay";
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riscv,isa = "rv32imafdcxandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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CPU1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU2: cpu@2 {
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compatible = "riscv";
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device_type = "cpu";
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reg = <2>;
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status = "okay";
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riscv,isa = "rv32imafdcxandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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CPU2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU3: cpu@3 {
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compatible = "riscv";
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device_type = "cpu";
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reg = <3>;
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status = "okay";
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riscv,isa = "rv32imafdcxandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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CPU3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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dram: memory@0 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00000000 0x40000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "andestech,ae350";
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ranges;
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plic0: interrupt-controller@e4000000 {
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compatible = "sifive,plic-1.0.0";
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#address-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = < 0xe4000000 0x00001000
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0xe4002000 0x00000800
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0xe4200000 0x00010000 >;
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reg-names = "prio", "irq_en", "reg";
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riscv,max-priority = <255>;
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riscv,ndev = <1023>;
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interrupts-extended = <&CPU0_intc 11 &CPU1_intc 11
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&CPU2_intc 11 &CPU3_intc 11>;
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};
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plic_sw0: interrupt-controller@e6400000 {
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compatible = "andestech,plic_sw";
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#address-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6400000 0x00400000>;
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riscv,max-priority = <255>;
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riscv,ndev = <1023>;
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interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3
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&CPU2_intc 3 &CPU3_intc 3>;
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};
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smu: smu@f0100000 {
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compatible = "andestech,atcsmu100";
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reg = <0xf0100000 0x1000>;
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status = "disabled";
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};
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l2_cache: cache-controller@e0500000 {
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compatible = "andestech,l2c";
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reg = <0xe0500000 0x1000>;
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cache-unified;
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status = "disabled";
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};
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uart0: serial@f0200020 {
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compatible = "ns16550";
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label = "UART_0";
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reg = <0xf0200020 0x1000>;
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reg-shift = <2>;
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interrupts = <8 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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uart1: serial@f0300020 {
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compatible = "ns16550";
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label = "UART_1";
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reg = <0xf0300020 0x1000>;
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reg-shift = <2>;
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interrupts = <9 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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pit0: pit@f0400000 {
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compatible = "andestech,atcpit100";
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label = "PIT_0";
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reg = <0xf0400000 0x1000>;
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interrupts = <3 1>;
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interrupt-parent = <&plic0>;
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clock-frequency = <60000000>;
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status = "disabled";
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};
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rtc0: rtc@f0600000 {
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compatible = "andestech,atcrtc100";
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reg = <0xf0600000 0x1000>;
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interrupts = <1 1>, <2 1>;
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interrupt-parent = <&plic0>;
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wakeup-source;
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status = "disabled";
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};
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gpio0: gpio@f0700000 {
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compatible = "andestech,atcgpio100";
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label = "GPIO_0";
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reg = <0xf0700000 0x1000>;
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interrupts = <7 1>;
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interrupt-parent = <&plic0>;
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gpio-controller;
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ngpios = <32>;
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#gpio-cells = <2>;
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status = "disabled";
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};
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i2c0: i2c@f0a00000 {
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compatible = "andestech,atciic100";
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label = "I2C_0";
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reg = <0xf0a00000 0x1000>;
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interrupts = <6 1>;
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interrupt-parent = <&plic0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@f0b00000 {
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compatible = "andestech,atcspi200";
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label = "SPI_0";
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reg = <0xf0b00000 0x1000
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0x80000000 DT_SIZE_K(1024)>;
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reg-names = "control", "mem";
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interrupts = <4 1>;
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interrupt-parent = <&plic0>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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clock-frequency = <66000000>;
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status = "disabled";
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};
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spi1: spi@f0f00000 {
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compatible = "andestech,atcspi200";
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label = "SPI_1";
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reg = <0xf0f00000 0x1000>;
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reg-names = "control";
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interrupts = <5 1>;
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interrupt-parent = <&plic0>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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clock-frequency = <66000000>;
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status = "disabled";
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};
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dma0: dma@f0c00000 {
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compatible = "andestech,atcdmac300";
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reg = <0xf0c00000 0x1000>;
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interrupts = <10 1>;
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interrupt-parent = <&plic0>;
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dma-channels = <8>;
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};
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eth0: eth@e0100000 {
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compatible = "andestech,atfmac100";
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label = "ETH_0";
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reg = <0xe0100000 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&plic0>;
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local-mac-address = [FC 8C EB 9B A6 51];
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status = "disabled";
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};
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lcd0: lcd@e0200000 {
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compatible = "andestech,atflcdc100";
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label = "LCD_0";
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reg = <0xe0200000 0x1000>;
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interrupts = <20 1>;
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interrupt-parent = <&plic0>;
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clock-frequency = <30000000>;
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status = "disabled";
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};
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smc0: smc@e0400000 {
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compatible = "andestech,atfsmc020";
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reg = <0xe0400000 0x1000>;
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status = "disabled";
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};
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snd0: snd@f0d00000 {
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compatible = "andestech,atfac97";
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reg = <0xf0d00000 0x1000>;
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interrupts = <17 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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mmc0: mmc@f0e00000 {
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compatible = "andestech,atfsdc010";
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reg = <0xf0e00000 0x1000>;
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interrupts = <18 1>;
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interrupt-parent = <&plic0>;
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cap-sd-highspeed;
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max-frequency = <100000000>;
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clock-freq-min-max = <400000 100000000>;
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fifo-depth = <0x10>;
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status = "disabled";
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};
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};
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};
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