From e8b29aae3522272d1cb2ea8bbe5601f8ffef5426 Mon Sep 17 00:00:00 2001 From: Furkan Akkiz Date: Thu, 2 Jan 2025 10:35:16 +0300 Subject: [PATCH] boards: adi: Update MAX78002EVKIT index.rst file - Removed unrelated information with MAX78002EVKIT. - Updated "Connections and IOs" part's format. Signed-off-by: Furkan Akkiz --- boards/adi/max78002evkit/doc/index.rst | 458 +++++++++++++++++-------- 1 file changed, 319 insertions(+), 139 deletions(-) diff --git a/boards/adi/max78002evkit/doc/index.rst b/boards/adi/max78002evkit/doc/index.rst index a5bd4acf09b..a57c1e28d12 100644 --- a/boards/adi/max78002evkit/doc/index.rst +++ b/boards/adi/max78002evkit/doc/index.rst @@ -42,7 +42,7 @@ Hardware - MIPI Camera Serial Interface 2 (MIPI CSI-2) Controller V2.1 - Support for Two Data Lanes - 12-Bit Parallel Camera Interface - - I 2S Controller/Target for Digital Audio Interface + - I2S Controller/Target for Digital Audio Interface - Secure Digital Interface Supports SD 3.0/SDIO 3.0/eMMC 4.51 - Convolutional Neural Network (CNN) Accelerator @@ -71,51 +71,6 @@ Hardware - AES 128/192/256 Hardware Acceleration Engine - True Random Number Generator (TRNG) Seed Generator - - Ultra-Low-Power Wireless Microcontroller - - - Internal 100MHz Oscillator - - Flexible Low-Power Modes with 7.3728MHz System Clock Option - - 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank) - - 16KB Instruction Cache - - - Bluetooth 5.2 LE Radio - - - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing - - Fully Open-Source Bluetooth 5.2 Stack Available - - Supports AoA, AoD, LE Audio, and Mesh - - High-Throughput (2Mbps) Mode - - Long-Range (125kbps and 500kbps) Modes - - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm - - Single-Ended Antenna Connection (50Ω) - - - Power Management Maximizes Battery Life - - - 2.0V to 3.6V Supply Voltage Range - - Integrated SIMO Power Regulator - - Dynamic Voltage Scaling (DVS) - - 23.8μA/MHz Active Current at 3.0V - - 4.4μA at 3.0V Retention Current for 32KB - - Selectable SRAM Retention + RTC in Low-Power Modes - - - Multiple Peripherals for System Control - - - Up to Two High-Speed SPI Master/Slave - - Up to Three High-Speed I2C Master/Slave (3.4Mbps) - - Up to Four UART, One I2S Master/Slave - - Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps - - Up to Four Micro-Power Comparators - - Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers - - 1-Wire® Master - - Up to Four Pulse Train (PWM) Engines - - RTC with Wake-Up Timer - - Up to 52 GPIOs - - - Security and Integrity​ - - - Available Secure Boot - - TRNG Seed Generator - - AES 128/192/256 Hardware Acceleration Engine - - External devices connected to the MAX78002 EVKIT: - Color TFT Display @@ -165,99 +120,324 @@ The ``max78002evkit/max78002/m4`` board target supports the following interfaces Connections and IOs =================== -+-----------+-------------------+----------------------------------------------------------------------------------+ -| Name | Signal | Usage | -+===========+===================+==================================================================================+ -| JP1 | 3V3 MON | Normal operation in conjunction with JP3 jumpered 1-2 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP2 | 3V3 SW PM BYPASS | Power monitor shunts for main 3.3 V system power are bypassed | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP3 | CNN MON | Normal operation in conjunction with JP6 jumpered 1-2 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP4 | VCOREA PM BYPASS | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP5 | VCOREB PM BYPASS | Power monitor shunts for VCOREB are bypassed | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP6 | VREGO_A PM BYPASS | Power monitor shunts for VREGO_A are bypassed | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP7 | VBAT | Enable/Disable 3V3 VBAT power | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP8 | VREGI | Enable/Disable 3V3 VREGI power | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP9 | VREGI/VBAT | Onboard 3V3_PM / external source at TP10 supplies VREGI/VBAT | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP10 | VDDIOH | Onboard 3V3_PM/3V3_SW supplies VDDIOH | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP11 | VDDA | VREGO_A_PM powers VDDA | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP12 | VDDIO | VREGO_A_PM powers VDDIO | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP13 | VCOREB | VREGO_B powers VCOREB | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP14 | VCOREA | VREGO_C ties to net VCOREA | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP15 | VREF | DUT ADC VREF is supplied by precision external reference | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP16 | I2C1 SDA | I2C1 DATA pull-up | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP17 | I2C1 SCL | I2C1 CLOCK pull-up | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP18 | TRIG1 | PWR accumulator trigger signal 1 ties to port 1.6 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP19 | TRIG2 | PWR accumulator trigger signal 2 ties to port 1.7 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP20 | UART0 EN | Connect/Disconnect USB-UART bridge to UART0 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP21 | I2C0_SDA | I2C0 DATA pull-up | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP22 | I2C0_SCL | I2C0 CLOCK pull-up | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP23 | UART1 EN | Connect/Disconnect USB-UART bridge to UART1 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP24 | EXT I2C0 EN | Enable/Disable QWIIC interface for I2C0 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP25 | PB1 PU | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.6 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP26 | PB2 PU | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.7 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP27 | I2C2 SDA | I2C2 DATA pull-up | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP28 | I2C2 SCL | I2C2 CLOCK pull-up | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP29 | VDDB | USB XCVR VDDB powered from VBUS / powered full time by system 3V3_PM | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP30 | EXT I2C2 EN | Enable/Disable QWIIC interface for I2C2 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP31 | L/R SEL | Select MIC ON R/L CH, I2S microphone data stream | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP32 | MIC-I2S I/O | External I2S/MIC data from I2S I/O / MIC header connected to I2S SDI | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP33 | MIC-I2S/CODEC | Onboard CODEC data / external I2S data from header connects to I2S SDI | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP34 | I2S VDD | Select 1.8V/3.3V for external MIC and DATA I2S interface | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP35 | I2C1 SDA | I2C1 DATA pull-up | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP36 | I2C1 SCL | I2C1 CLOCK pull-up | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP37 | I2S CK SEL | Select SMA connector J6 / onboard crystal oscillator for I2S master clock source | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP38 | DVP CAM PWR | Enable/Disable OVM7692 for DVP camera PWDN input | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP39 | SW CAM PWUP | Camera reset and power up under port pin control | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP40 | HW PWUP / SW PWUP | Camera will reset and power up as soon as 3.3V reaches a valid level | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP41 | CSI CAM I2C EN | Connect/Disconnect I2C1 to CSI camera Digilent P5C I2C | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP42 | TFT DC | TFT data/command select connects to port 2.2 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP43 | TFT CS | Select port 0.3 / port 1.7 to drive TFT CS | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP44 | LED1 EN | Enable/Disable LED1 | -+-----------+-------------------+----------------------------------------------------------------------------------+ -| JP45 | LED2 EN | Enable/Disable LED2 | -+-----------+-------------------+----------------------------------------------------------------------------------+ ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| Name | Name | Settings | Description | ++===========+===================+===============+==================================================================================================+ +| JP1 | 3V3 MON | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Normal operation in conjunction with JP3 jumpered 1-2 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Test access point for current measurement | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP2 | 3V3 SW PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Power monitor shunts for main 3.3 V system power are bypassed | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Main 3.3V input routes through shunts for power accumulator measurements | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP3 | CNN MON | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Normal operation in conjunction with JP6 jumpered 1-2 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Test access point for current measurement of U4's share of VCOREA and CNN loads | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP4 | VCOREA PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | VCOREA + CNN loads route through shunts for power accumulator | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP5 | VCOREB PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Power monitor shunts for VCOREB are bypassed | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | VCOREB power routes through shunts for power accumulator | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP6 | VREGO_A PM BYPASS | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Power monitor shunts for VREGO_A are bypassed | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | VREGO_A power routes through shunts for power accumulator | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP7 | VBAT | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables 3V3 VBAT power | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Disables 3V3 VBAT power | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP8 | VREGI | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Enables 3V3 VREGI power | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Disables 3V3 VREGI power | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP9 | VREGI/VBAT | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Onboard 3V3_PM supplies VREGI/VBAT | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-3 | | | External source at TP10 supplies VREGI/VBAT | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP10 | VDDIOH | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Onboard 3V3_PM supplies VDDIOH | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Onboard 3V3_SW supplies VDDIOH | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP11 | VDDA | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | VREGO_A_PM powers VDDA | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | VDDA may be powered using TP6 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP12 | VDDIO | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | VREGO_A_PM powers VDDIO | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | VDDIO may be powered using TP7 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP13 | VCOREB | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | VREGO_B powers VCOREB | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | VCOREB may be powered using TP8 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP14 | VCOREA | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | VREGO_C ties to net VCOREA | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Net VCOREA may be powered using TP9; JP17 may also be used as a current test point | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP15 | VREF | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | DUT ADC VREF is supplied by precision external reference | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | External ADC VREF disabled; ref voltage may be injected at JP18.1 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP16 | I2C1 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2C1 DATA pullup | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Close this jumper as needed to assure proper termination | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP17 | I2C1 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2C1 CLOCK pullup | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Close this jumper as needed to assure proper termination | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP18 | TRIG1 | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | PWR accumulator trigger signal 1 ties to port 1.6 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | TRIG1 is disabled, so DVP camera PCIF_D10 may be used instead | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP19 | TRIG2 | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | PWR accumulator trigger signal 2 ties to port 1.7 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | TRIG2 is disabled, so DVP camera PCIF_D11 may be used instead | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP20 | UART0 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Closed | | | USB-UART bridge connected to DUT UART0 (RTS and CTS are supported) | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | USB-UART bridge disconnected from DUT UART0 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP21 | I2C0_SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2C0 DATA pull-up | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Close this jumper as needed to assure proper termination | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP22 | I2C0_SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2C0 CLOCK pull-up | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Close this jumper as needed to assure proper termination | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP23 | UART1 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Closed | | | USB-UART bridge connected to DUT UART1 (no HW flow control) | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | USB-UART bridge disconnected from DUT UART1 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP24 | EXT I2C0 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | QWIIC interface for I2C0 enabled by default | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Open this jumper to place the QWIIC level translator into a high-Z state | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP25 | PB1 PU | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | 100kΩ pull-up enabled for pushbutton mode, port 2.6 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Pull-up disabled, allowing port pin to be repurposed (this port shared with AIN6) | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP26 | PB2 PU | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | 100kΩ pull-up enabled for pushbutton mode, port 2.7 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Pull-up disabled, allowing port pin to be repurposed (this port shared with AIN7) | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP27 | I2C2 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2C2 DATA pull-up | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Close this jumper as needed to assure proper termination | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP28 | I2C2 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2C2 CLOCK pull-up | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Close this jumper as needed to assure proper termination | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP29 | VDDB | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-1 | | | DUT USB XCVR VDDB powered from VBUS regulated with dedicated 3.3V LDO | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-3 | | | USB XCVR VDDB powered full time by system 3V3_PM | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP30 | EXT I2C2 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | QWIIC interface for I2C2 enabled by default | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Open this jumper to place the QWIIC level translator into a high-Z state | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP31 | L/R SEL | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | MIC ON R CH, I2S microphone data stream | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | MIC ON L CH, I2S microphone data stream | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP32 | MIC-I2S I/O | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | External I2S data from I2S I/O header connected to I2S SDI. | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | External MIC data from I2S MIC header connected to I2S SDI | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP33 | MIC-I2S/CODEC | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Onboard CODEC data connects to I2S SDI | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | External I2S data (mic or slave I2S) from header connects to I2S SDI | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP34 | I2S VDD | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-1 | | | External MIC and DATA I2S interface headers run at 1.8V | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-3 | | | External MIC and DATA I2S interface headers run at 3.3V | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP35 | I2C1 SDA | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2C1 DATA pull-up | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Close this jumper as needed to assure proper termination | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP36 | I2C1 SCL | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2C1 CLOCK pull-up | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Close this jumper as needed to assure proper termination | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP37 | I2S CK SEL | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | I2S master clock sourced from SMA connector J6 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | I2S master clock sourced from onboard crystal oscillator | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP38 | DVP CAM PWR | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-1 | | | Sets state of DVP camera PWDN input; default is OFF for OVM7692 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-3 | | | Sets state of DVP camera PWDN input; 2-3 will power up OVM7692 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP39 | SW CAM PWUP | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Camera reset and power up under port pin control | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Digilent P5C camera powered down, JP39 can over ride this condition | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP40 | HW PWUP / SW PWUP | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | Camera will reset and power up as soon as 3.3V reaches a valid level | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Camera reset and power up under port pin control if JP39 is installed; else, camera off | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP41 | CSI CAM I2C EN | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | CSI camera Digilent P5C I2C connects to I2C1 for register setup | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Level translator and I2C PU are in high-Z state; I2C1 disconnected from P5C registers | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP42 | TFT DC | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | TFT data/command select connects to port 2.2 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Pull jumper if using AIN2 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP43 | TFT CS | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-1 | | | TFT CS driven by port 0.3, shared with UART0 RTS | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 2-3 | | | TFT CS driven by port 1.7, shared with DVP DATA 11 and TRIG2 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP44 | LED1 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | LED0 illuminates when port 2.4 is high | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Pull jumper if using AIN4 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ +| JP45 | LED2 EN | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | 1-2 | | | LED1 illuminates when port 2.5 is high | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | Open | | | Pull jumper if using AIN5 | | +| | | +-----------+ | +-----------------------------------------------------------------------------------------+ | +| | | | | ++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+ Programming and Debugging *************************