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drivers: ethernet: xlnx: gem: do not lock/unlock the SLCRs

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Do not lock/unlock the System Level Control Registers (SLCRs) in the Xilinx
GEM ethernet driver. The SLRCs are unlocked once at boot time.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen 2022-06-21 13:06:18 +02:00 committed by Carles Cufí
parent 982d379808
commit ea433a4803
2 changed files with 0 additions and 16 deletions
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8
drivers/ethernet/eth_xlnx_gem.c
View file

@ -829,15 +829,7 @@ static void eth_xlnx_gem_configure_clocks(const struct device *dev)
((div1 & ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK) <<
ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR1_SHIFT);
/*
* SLCR must be unlocked prior to and locked after writing to
* the clock configuration register.
*/
sys_write32(ETH_XLNX_SLCR_UNLOCK_KEY,
ETH_XLNX_SLCR_UNLOCK_REGISTER_ADDRESS);
sys_write32(clk_ctrl_reg, dev_conf->clk_ctrl_reg_address);
sys_write32(ETH_XLNX_SLCR_LOCK_KEY,
ETH_XLNX_SLCR_LOCK_REGISTER_ADDRESS);
#endif /* CONFIG_SOC_XILINX_ZYNQMP / CONFIG_SOC_FAMILY_XILINX_ZYNQ7000 */
LOG_DBG("%s set clock dividers div0/1 %u/%u for target "

8
drivers/ethernet/eth_xlnx_gem_priv.h
View file

@ -114,19 +114,11 @@
/*
* Zynq-7000 TX clock configuration:
*
* SLCR unlock & lock registers, magic words:
* comp. Zynq-7000 TRM, chapter B.28, registers SLCR_LOCK and SLCR_UNLOCK,
* p. 1576f.
*
* GEMx_CLK_CTRL (SLCR) registers:
* [25 .. 20] Reference clock divisor 1
* [13 .. 08] Reference clock divisor 0
* [00] Clock active bit
*/
#define ETH_XLNX_SLCR_LOCK_REGISTER_ADDRESS 0xF8000004
#define ETH_XLNX_SLCR_UNLOCK_REGISTER_ADDRESS 0xF8000008
#define ETH_XLNX_SLCR_LOCK_KEY 0x767B
#define ETH_XLNX_SLCR_UNLOCK_KEY 0xDF0D
#define ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR_MASK 0x0000003F
#define ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR1_SHIFT 20
#define ETH_XLNX_SLCR_GEMX_CLK_CTRL_DIVISOR0_SHIFT 8