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drivers: ssp: fix program of MLCS register

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Programming of the MLCS register was performed on the incorrect bits.
Additionally, saving the new version did not erase the previously set
value, which could result in an incorrect register value.

Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit is contained in:
Damian Nikodem 2024-07-24 10:08:47 +02:00 committed by Carles Cufí
parent 65bdf6564b
commit ed31037d5f
5 changed files with 12 additions and 8 deletions
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11
drivers/dai/intel/ssp/ssp.c
View file

@ -1962,15 +1962,16 @@ static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, s
case SSP_LINK_CLK_SOURCE: case SSP_LINK_CLK_SOURCE:
#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE #ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
link = (struct ssp_intel_link_ctl *)&aux_tlv->val; link = (struct ssp_intel_link_ctl *)&aux_tlv->val;
#if CONFIG_SOC_INTEL_ACE15_MTPM #if CONFIG_SOC_INTEL_ACE15_MTPM
sys_write32(sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) | sys_write32((sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) &
~I2CLCTL_MLCS(0x7)) |
I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) + I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
I2SLCTL_OFFSET); I2SLCTL_OFFSET);
#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL #elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
sys_write32(sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) | sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) &
I2CLCTL_MLCS(link->clock_source), dai_i2svss_base(dp) + ~I2CLCTL_MLCS(0x7)) |
I2SLCTL_OFFSET); I2CLCTL_MLCS(link->clock_source),
dai_i2svss_base(dp) + I2SLCTL_OFFSET);
#endif #endif
LOG_INF("link clock_source %u", link->clock_source); LOG_INF("link clock_source %u", link->clock_source);
#endif #endif

2
drivers/dai/intel/ssp/ssp_regs_v1.h
View file

@ -215,7 +215,7 @@
#define I2SLCTL_SPA(x) BIT(0 + x) #define I2SLCTL_SPA(x) BIT(0 + x)
#define I2SLCTL_CPA(x) BIT(8 + x) #define I2SLCTL_CPA(x) BIT(8 + x)
#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x) #define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(29, 27, x)
#define SHIM_CLKCTL 0x78 #define SHIM_CLKCTL 0x78
#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x)
#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x)

2
drivers/dai/intel/ssp/ssp_regs_v2.h
View file

@ -218,7 +218,7 @@
#define PCMS0CM_OFFSET 0x16 #define PCMS0CM_OFFSET 0x16
#define PCMS1CM_OFFSET 0x1A #define PCMS1CM_OFFSET 0x1A
#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x) #define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(29, 27, x)
#define SHIM_CLKCTL 0x78 #define SHIM_CLKCTL 0x78
#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x)
#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x)

2
drivers/dai/intel/ssp/ssp_regs_v3.h
View file

@ -215,7 +215,7 @@
#define I2SLCTL_SPA(x) BIT(16 + x) #define I2SLCTL_SPA(x) BIT(16 + x)
#define I2SLCTL_CPA(x) BIT(23 + x) #define I2SLCTL_CPA(x) BIT(23 + x)
#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x) #define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(29, 27, x)
#define SHIM_CLKCTL 0x78 #define SHIM_CLKCTL 0x78
#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x)
#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x)

3
dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
View file

@ -205,6 +205,7 @@
#size-cells = <0>; #size-cells = <0>;
reg = <0x00028100 0x1000 reg = <0x00028100 0x1000
0x00079C00 0x200>; 0x00079C00 0x200>;
i2svss = <0x00028C00 0x1000>;
interrupts = <0x00 0 0>; interrupts = <0x00 0 0>;
interrupt-parent = <&ace_intc>; interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 1 dmas = <&hda_link_out 1
@ -269,6 +270,7 @@
#size-cells = <0>; #size-cells = <0>;
reg = <0x00029100 0x1000 reg = <0x00029100 0x1000
0x00079C00 0x200>; 0x00079C00 0x200>;
i2svss = <0x00029C00 0x1000>;
interrupts = <0x01 0 0>; interrupts = <0x01 0 0>;
interrupt-parent = <&ace_intc>; interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 2 dmas = <&hda_link_out 2
@ -333,6 +335,7 @@
#size-cells = <0>; #size-cells = <0>;
reg = <0x0002a100 0x1000 reg = <0x0002a100 0x1000
0x00079C00 0x200>; 0x00079C00 0x200>;
i2svss = <0x0002AC00 0x1000>;
interrupts = <0x02 0 0>; interrupts = <0x02 0 0>;
interrupt-parent = <&ace_intc>; interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 3 dmas = <&hda_link_out 3