adafruit-mirror/zephyr
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 8

x86: apic: use device MMIO APIs

Browse source 
A hack was required for the loapic code due to the address
range not being in DTS. A bug was filed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2020-06-26 12:09:01 -07:00 committed by Carles Cufí
parent d15a531197
commit ee3c50ba6d
5 changed files with 51 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
arch/x86/core/ia32/intstub.S
View file

@ -209,8 +209,13 @@ alreadyOnIntStack:
movl $(X86_X2APIC_BASE_MSR + (LOAPIC_EOI >> 4)), %ecx
wrmsr
#else /* xAPIC */
#ifdef DEVICE_MMIO_IS_IN_RAM
movl z_loapic_regs, %edx
movl %eax, LOAPIC_EOI(%edx)
#else
movl %eax, (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
#endif
#endif /* DEVICE_MMIO_IS_IN_RAM */
#endif /* CONFIG_X2APIC */
/* determine whether exiting from a nested interrupt */
movl $_kernel, %ecx

7
arch/x86/core/intel64/locore.S
View file

@ -698,8 +698,13 @@ irq_dispatch:
movl $(X86_X2APIC_BASE_MSR + (LOAPIC_EOI >> 4)), %ecx
wrmsr
#else /* xAPIC */
#ifdef DEVICE_MMIO_IS_IN_RAM
movl z_loapic_regs, %edx
movl %eax, LOAPIC_EOI(%edx)
#else
movl %eax, (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
#endif
#endif /* DEVICE_MMIO_IS_IN_RAM */
#endif /* CONFIG_X2APIC */
movq %gs:__x86_tss64_t_cpu_OFFSET, %rsi

7
drivers/interrupt_controller/intc_ioapic.c
View file

@ -64,7 +64,9 @@
#include <drivers/interrupt_controller/loapic.h> /* public API declarations and registers */
#include "intc_ioapic_priv.h"
#define IOAPIC_REG DT_INST_REG_ADDR(0)
DEVICE_MMIO_TOPLEVEL_STATIC(ioapic_regs, 0);
#define IOAPIC_REG DEVICE_MMIO_TOPLEVEL_GET(ioapic_regs)
#define BITS_PER_IRQ 4
#define IOAPIC_BITFIELD_HI_LO 0
#define IOAPIC_BITFIELD_LVL_EDGE 1
@ -121,6 +123,9 @@ static void IoApicRedUpdateLo(unsigned int irq, uint32_t value,
int ioapic_init(struct device *unused)
{
ARG_UNUSED(unused);
DEVICE_MMIO_TOPLEVEL_MAP(ioapic_regs, K_MEM_CACHE_NONE);
#ifdef CONFIG_IOAPIC_MASK_RTE
int32_t ix; /* redirection table index */
uint32_t rteValue; /* value to copy into redirection table entry */

13
drivers/interrupt_controller/intc_loapic.c
View file

@ -65,6 +65,15 @@ uint32_t loapic_suspend_buf[LOPIC_SUSPEND_BITS_REQD / 32] = {0};
static uint32_t loapic_device_power_state = DEVICE_PM_ACTIVE_STATE;
#endif
#ifdef DEVICE_MMIO_IS_IN_RAM
mm_reg_t z_loapic_regs;
#endif
void send_eoi(void)
{
x86_write_xapic(LOAPIC_EOI, 0);
}
/**
* @brief Enable and initialize the local APIC.
*
@ -75,6 +84,10 @@ void z_loapic_enable(unsigned char cpu_number)
{
int32_t loApicMaxLvt; /* local APIC Max LVT */
#ifdef DEVICE_MMIO_IS_IN_RAM
device_map(&z_loapic_regs, CONFIG_LOAPIC_BASE_ADDRESS, 0x1000,
K_MEM_CACHE_NONE);
#endif /* DEVICE_MMIO_IS_IN_RAM */
#ifndef CONFIG_X2APIC
/*
* in xAPIC and flat model, bits 24-31 in LDR (Logical APIC ID) are

22
include/drivers/interrupt_controller/loapic.h
View file

@ -11,6 +11,7 @@
#include <arch/cpu.h>
#include <arch/x86/msr.h>
#include <sys/device_mmio.h>
/* Local APIC Register Offset */
@ -70,6 +71,11 @@ static inline uint64_t x86_read_x2apic(unsigned int reg)
return z_x86_msr_read(X86_X2APIC_BASE_MSR + reg);
}
/* Defined in intc_loapic.c */
#ifdef DEVICE_MMIO_IS_IN_RAM
extern mm_reg_t z_loapic_regs;
#endif
/**
* @brief Read 32-bit value from the local APIC in xAPIC (MMIO) mode.
*
@ -77,7 +83,13 @@ static inline uint64_t x86_read_x2apic(unsigned int reg)
*/
static inline uint32_t x86_read_xapic(unsigned int reg)
{
return sys_read32(CONFIG_LOAPIC_BASE_ADDRESS + reg);
mm_reg_t base;
#ifdef DEVICE_MMIO_IS_IN_RAM
base = z_loapic_regs;
#else
base = CONFIG_LOAPIC_BASE_ADDRESS;
#endif
return sys_read32(base + reg);
}
/**
@ -119,7 +131,13 @@ static inline void x86_write_x2apic(unsigned int reg, uint64_t val)
*/
static inline void x86_write_xapic(unsigned int reg, uint32_t val)
{
sys_write32(val, CONFIG_LOAPIC_BASE_ADDRESS + reg);
mm_reg_t base;
#ifdef DEVICE_MMIO_IS_IN_RAM
base = z_loapic_regs;
#else
base = CONFIG_LOAPIC_BASE_ADDRESS;
#endif
sys_write32(val, base + reg);
}
/**