diff --git a/dts/bindings/cpu/riscv,it8xxx2.yaml b/dts/bindings/cpu/riscv,it8xxx2.yaml new file mode 100644 index 00000000000..c7f94a424b2 --- /dev/null +++ b/dts/bindings/cpu/riscv,it8xxx2.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: ITE IT8XXX2 RISC-V CPU + +compatible: "riscv-ite" + +include: cpu.yaml diff --git a/dts/bindings/flash_controller/ite,it8xxx2-flash-controller.yaml b/dts/bindings/flash_controller/ite,it8xxx2-flash-controller.yaml new file mode 100644 index 00000000000..16da0e5d964 --- /dev/null +++ b/dts/bindings/flash_controller/ite,it8xxx2-flash-controller.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: ITE IT8XXX2 flash memory + +compatible: "ite,it8xxx2-flash-controller" + +include: flash-controller.yaml diff --git a/dts/bindings/gpio/ite,it8xxx2-gpio.yaml b/dts/bindings/gpio/ite,it8xxx2-gpio.yaml new file mode 100644 index 00000000000..bf3061f6e52 --- /dev/null +++ b/dts/bindings/gpio/ite,it8xxx2-gpio.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: This binding gives a base representation of the ITE gpio + +compatible: "ite,it8xxx2-gpio" + +include: [gpio-controller.yaml, base.yaml] + +properties: + port-is-output: + type: boolean + description: Indicates if the port is an output port + + reg: + required: true + + label: + required: true + +gpio-cells: + - pin + - flags diff --git a/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml b/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml new file mode 100644 index 00000000000..54c932d8931 --- /dev/null +++ b/dts/bindings/interrupt-controller/ite,it8xxx2-intc.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: ITE Interrupt controller +compatible: "ite,it8xxx2-intc" + +include: [interrupt-controller.yaml, base.yaml] + +properties: + reg: + required: true + +interrupt-cells: + - irq + - flags diff --git a/dts/bindings/pinctrl/ite,it8xxx2-pinmux.yaml b/dts/bindings/pinctrl/ite,it8xxx2-pinmux.yaml new file mode 100644 index 00000000000..eae67a8183b --- /dev/null +++ b/dts/bindings/pinctrl/ite,it8xxx2-pinmux.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: ITE IT8XXX2 pinmux node + +compatible: "ite,it8xxx2-pinmux" + +include: base.yaml + +properties: + reg: + required: true + + label: + required: true diff --git a/dts/bindings/spi/ite,it8xxx2-sspi.yaml b/dts/bindings/spi/ite,it8xxx2-sspi.yaml new file mode 100644 index 00000000000..0653617b9f5 --- /dev/null +++ b/dts/bindings/spi/ite,it8xxx2-sspi.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: IT8XXX2 SPI + +compatible: "ite,it8xxx2-sspi" + +include: spi-controller.yaml + +properties: + reg: + required: true + + interrupts: + required: true diff --git a/dts/bindings/timer/ite,it8xxx2-timer.yaml b/dts/bindings/timer/ite,it8xxx2-timer.yaml new file mode 100644 index 00000000000..73701ce1dac --- /dev/null +++ b/dts/bindings/timer/ite,it8xxx2-timer.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: ITE Ext-timer + +compatible: "ite,it8xxx2-timer" + +include: base.yaml + +properties: + reg: + required: true + + interrupts: + required: true + + label: + required: true diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index b17b76b4366..bef971823c1 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -210,6 +210,7 @@ iom Iomega Corporation isee ISEE 2007 S.L. isil Intersil issi Integrated Silicon Solutions Inc. +ite ITE Tech. Inc. itead ITEAD Intelligent Systems Co.Ltd iwave iWave Systems Technologies Pvt. Ltd. jdi Japan Display Inc. diff --git a/dts/riscv/it8xxx2.dtsi b/dts/riscv/it8xxx2.dtsi new file mode 100644 index 00000000000..4d599f2502a --- /dev/null +++ b/dts/riscv/it8xxx2.dtsi @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2020 ITE Corporation. All Rights Reserved. + * Copyright (c) 2019-2020 Jyunlin Chen + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "ite,riscv-ite"; + device_type = "cpu"; + reg = <0>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flashctrl: flash-controller@80000000 { + compatible = "ite,it8xxx2-flash-controller"; + reg = <0x80000000 0x100>; + label = "fspi"; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@80000000 { + compatible = "soc-nv-flash"; + reg = <0x80000000 DT_SIZE_K(512)>; + erase-block-size = <1024>; + write-block-size = <1>; + }; + }; + pinmux: pinmux@f016f0 { + compatible = "ite,it8xxx2-pinmux"; + reg = <0x00f016f0 0x0010>; + label = "PINMUX"; + }; + sram0: memory@80080000 { + compatible = "mmio-sram"; + reg = <0x80080000 DT_SIZE_K(60)>; + }; + intc: interrupt-controller@f03f00 { + #interrupt-cells = <2>; + compatible = "ite,it8xxx2-intc"; + interrupt-controller; + reg = <0x00f03f00 0x0100>; + }; + uart1: uart@f02700 { + compatible = "ns16550"; + reg = <0x00f02700 0x0020>; + label = "console"; + current-speed = <115200>; + clock-frequency = <1804800>; + interrupts = <38 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; + }; + uart2: uart@f02800 { + compatible = "ns16550"; + reg = <0x00f02800 0x0020>; + label = "UART_2"; + current-speed = <460800>; + clock-frequency = <1804800>; + interrupts = <39 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; + }; + timer: timer@f01f00 { + compatible = "ite,it8xxx2-timer"; + reg = <0x00f01f00 0x0062>; + label = "sys_clock"; + interrupts = <0 IRQ_TYPE_NONE + 30 IRQ_TYPE_EDGE_RISING + 58 IRQ_TYPE_EDGE_RISING + 155 IRQ_TYPE_EDGE_FALLING + 156 IRQ_TYPE_EDGE_FALLING + 157 IRQ_TYPE_EDGE_FALLING + 158 IRQ_TYPE_EDGE_FALLING + 159 IRQ_TYPE_EDGE_FALLING + 80 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; + }; + gpiob: gpio@f01602 { + compatible = "ite,it8xxx2-gpio"; + reg = <0x00f01602 0x0001>; + ngpios = <8>; + label = "GPDRB"; + status = "disabled"; + gpio-controller; + interrupts = <106 IRQ_TYPE_LEVEL_HIGH + 107 IRQ_TYPE_LEVEL_HIGH + 92 IRQ_TYPE_LEVEL_HIGH + 108 IRQ_TYPE_LEVEL_HIGH + 99 IRQ_TYPE_LEVEL_HIGH + 109 IRQ_TYPE_LEVEL_HIGH + 110 IRQ_TYPE_LEVEL_HIGH + 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + #gpio-cells = <2>; + }; + gpiof: gpio@f01606 { + compatible = "ite,it8xxx2-gpio"; + reg = <0x00f01606 0x0001>; + ngpios = <8>; + label = "GPDRF"; + status = "disabled"; + gpio-controller; + interrupts = <101 IRQ_TYPE_LEVEL_HIGH + 102 IRQ_TYPE_LEVEL_HIGH + 103 IRQ_TYPE_LEVEL_HIGH + 104 IRQ_TYPE_LEVEL_HIGH + 52 IRQ_TYPE_LEVEL_HIGH + 53 IRQ_TYPE_LEVEL_HIGH + 54 IRQ_TYPE_LEVEL_HIGH + 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + #gpio-cells = <2>; + }; + gpiom: gpio@f0160D { + compatible = "ite,it8xxx2-gpio"; + reg = <0x00f0160D 0x0001>; + ngpios = <8>; + label = "GPDRM"; + status = "disabled"; + gpio-controller; + interrupt-parent = <&intc>; + #gpio-cells = <2>; + }; + spi0:spi@f02600 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ite,it8xxx2-sspi"; + reg = <0x00f02600 0x40>; + label = "SPI0"; + interrupt-parent = <&intc>; + interrupts = <37 IRQ_TYPE_EDGE_RISING>; + clock-frequency = <115200>; + }; + spi1:spi@f02640 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ite,it8xxx2-sspi"; + reg = <0x00f02640 0x40>; + label = "SPI1"; + interrupts = <37 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; + status = "okay"; + }; + }; +};