dts: bindings: fix typo in (ethernet, gpio, i2c, interrupt-controller)

Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/ethernet, gpio, i2c and
interrupt-controller.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>

dts/bindings/ethernet/xlnx,gem.yaml

@@ -303,7 +303,7 @@ properties:
   multicast-hash:
     type: boolean
     description: |
-      Optional feature flag - Enable multicast hash. When set, mutlicast
+      Optional feature flag - Enable multicast hash. When set, multicast
       frames will be accepted when the 6 bit hash function of the desti-
       nation address points to a bit that is set in the hash register.
 

dts/bindings/gpio/richtek,rt1718s.yaml

@@ -5,7 +5,7 @@ description: |
     Richtek RT1718S TCPC chip
 
     The Richtek RT1718S chip is TCPC, but also has 3 pins, which can be used as
-    a usual GPIO. This node collects common proprties for RT1718S chip e.g. I2C
+    a usual GPIO. This node collects common properties for RT1718S chip e.g. I2C
     address. Feature-specific(GPIO, TCPC) properties should be placed in a child
     node e.g. a number of GPIOs.
 

dts/bindings/i2c/atmel,sam-i2c-twim.yaml

@@ -14,7 +14,7 @@ description: |
 
   When using speeds above standard mode, user may need adjust clock and data
   lines slew and strength parameters.  In general, slew 0 and minimal strength
-  is enougth for short buses and light loads.  As reference, the below
+  is enough for short buses and light loads.  As reference, the below
   is the lowest power configuration:
 
     std-clk-slew-lim = <0>;

dts/bindings/interrupt-controller/cypress,psoc6-intmux.yaml

@@ -28,7 +28,7 @@ description: |
   ...
   intmux[7] = {ch31, ch30, ch29, ch28}
 
-  In pratical terms, the Cortex-M0+ requires user to define all NVIC interrupt
+  In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
   sources and the proper NVIC interrupt order. With that, the system configures
   the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
   More information about it at PSoC-6 Architecture Technical Reference Manual,
@@ -60,7 +60,7 @@ description: |
   The interrupt can be enabled/disable at NVIC at line 20 as usual.
 
   Notes:
-  1) Multiple definitions will generate multiple interrutps
+  1) Multiple definitions will generate multiple interrupts
   2) The interrupt sources are shared between Cortex-M0+/M4. These means, can
      trigger action in parallel in both processors.
   3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels

dts/bindings/interrupt-controller/nuvoton,npcx-miwu.yaml

@@ -16,7 +16,7 @@ properties:
   "#miwu-cells":
     type: int
     required: true
-    description: Number of items to present a MIWU input souce specifier
+    description: Number of items to present a MIWU input source specifier
 
 miwu-cells:
   - group