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dts: riscv: litex-vexriscv: Update for 32-bit CSRs

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Use register addresses and sizes from 32-bit CSR version

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
This commit is contained in:
Michal Sieron 2022-05-23 15:16:23 +02:00 committed by Marti Bolivar
parent 95d867e8ed
commit f45acb7d5f
1 changed files with 17 additions and 17 deletions
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34
dts/riscv/riscv32-litex-vexriscv.dtsi
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@ -80,16 +80,16 @@
compatible = "litex,timer0";
interrupt-parent = <&intc0>;
interrupts = <1 0>;
reg = <0xe0002800 0x10
0xe0002810 0x10
reg = <0xe0002800 0x4
0xe0002804 0x4
0xe0002808 0x4
0xe000280c 0x4
0xe0002810 0x4
0xe0002814 0x4
0xe0002818 0x4
0xe000281c 0x4
0xe0002820 0x4
0xe0002824 0x4
0xe0002828 0x10
0xe0002838 0x4
0xe000283c 0x4
0xe0002840 0x4
0xe0002844 0x4
0xe0002848 0x20>;
0xe0002824 0x8>;
reg-names =
"load",
"reload",
@ -257,14 +257,14 @@
clock0: clock@82005000 {
compatible = "litex,clk";
label = "clock0";
reg = <0x82005000 0x4
0x82005004 0x4
0x82005008 0x4
0x8200500c 0x4
0x82005010 0x4
0x82005014 0x4
0x82005018 0x8
0x82005020 0x8>;
reg = <0xe0004800 0x4
0xe0004804 0x4
0xe0004808 0x4
0xe000480c 0x4
0xe0004810 0x4
0xe0004814 0x4
0xe0004818 0x4
0xe000481c 0x4>;
reg-names = "drp_reset",
"drp_locked",
"drp_read",