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soc: st: stm32U5/L5 series also have SWO line

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Add the SWO trace output to the stm32H5/H7RS/L5/U5/WB series

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2024-10-28 13:46:30 +01:00 committed by Mahesh Mahadevan
parent e516a2219b
commit f781d7a26f
3 changed files with 5 additions and 3 deletions
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6
soc/st/stm32/common/soc_config.c
View file

@ -28,7 +28,9 @@ static int st_stm32_common_config(void)
{
#ifdef CONFIG_LOG_BACKEND_SWO
/* Enable SWO trace asynchronous mode */
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32H5X)
#if defined(CONFIG_SOC_SERIES_STM32H5X) || defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || defined(CONFIG_SOC_SERIES_STM32U5X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
LL_DBGMCU_EnableTraceClock();
#endif
#if !defined(CONFIG_SOC_SERIES_STM32WBX) && defined(DBGMCU_CR_TRACE_IOEN)
@ -36,7 +38,6 @@ static int st_stm32_common_config(void)
#endif
#endif /* CONFIG_LOG_BACKEND_SWO */
#if defined(CONFIG_USE_SEGGER_RTT)
/* On some STM32 boards, for unclear reason,
* RTT feature is working with realtime update only when
@ -49,7 +50,6 @@ static int st_stm32_common_config(void)
__HAL_RCC_GPDMA1_CLK_ENABLE();
#endif /* __HAL_RCC_DMA1_CLK_ENABLE */
#endif /* CONFIG_USE_SEGGER_RTT */
/* On some STM32 boards, for unclear reason,

1
soc/st/stm32/stm32l5x/Kconfig
View file

@ -13,5 +13,6 @@ config SOC_SERIES_STM32L5X
select ARMV8_M_DSP
select CPU_CORTEX_M_HAS_DWT
select HAS_STM32CUBE
select HAS_SWO
select HAS_PM
select SOC_EARLY_INIT_HOOK

1
soc/st/stm32/stm32u5x/Kconfig
View file

@ -16,6 +16,7 @@ config SOC_SERIES_STM32U5X
select CPU_CORTEX_M_HAS_DWT
select HAS_STM32CUBE
select HAS_PM
select HAS_SWO
select HAS_POWEROFF
select SOC_EARLY_INIT_HOOK