soc: st: stm32U5/L5 series also have SWO line
Add the SWO trace output to the stm32H5/H7RS/L5/U5/WB series Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
parent
e516a2219b
commit
f781d7a26f
3 changed files with 5 additions and 3 deletions
|
|
@ -28,7 +28,9 @@ static int st_stm32_common_config(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_LOG_BACKEND_SWO
|
#ifdef CONFIG_LOG_BACKEND_SWO
|
||||||
/* Enable SWO trace asynchronous mode */
|
/* Enable SWO trace asynchronous mode */
|
||||||
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32H5X)
|
#if defined(CONFIG_SOC_SERIES_STM32H5X) || defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
|
||||||
|
defined(CONFIG_SOC_SERIES_STM32L5X) || defined(CONFIG_SOC_SERIES_STM32U5X) || \
|
||||||
|
defined(CONFIG_SOC_SERIES_STM32WBX)
|
||||||
LL_DBGMCU_EnableTraceClock();
|
LL_DBGMCU_EnableTraceClock();
|
||||||
#endif
|
#endif
|
||||||
#if !defined(CONFIG_SOC_SERIES_STM32WBX) && defined(DBGMCU_CR_TRACE_IOEN)
|
#if !defined(CONFIG_SOC_SERIES_STM32WBX) && defined(DBGMCU_CR_TRACE_IOEN)
|
||||||
|
|
@ -36,7 +38,6 @@ static int st_stm32_common_config(void)
|
||||||
#endif
|
#endif
|
||||||
#endif /* CONFIG_LOG_BACKEND_SWO */
|
#endif /* CONFIG_LOG_BACKEND_SWO */
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_USE_SEGGER_RTT)
|
#if defined(CONFIG_USE_SEGGER_RTT)
|
||||||
/* On some STM32 boards, for unclear reason,
|
/* On some STM32 boards, for unclear reason,
|
||||||
* RTT feature is working with realtime update only when
|
* RTT feature is working with realtime update only when
|
||||||
|
|
@ -49,7 +50,6 @@ static int st_stm32_common_config(void)
|
||||||
__HAL_RCC_GPDMA1_CLK_ENABLE();
|
__HAL_RCC_GPDMA1_CLK_ENABLE();
|
||||||
#endif /* __HAL_RCC_DMA1_CLK_ENABLE */
|
#endif /* __HAL_RCC_DMA1_CLK_ENABLE */
|
||||||
|
|
||||||
|
|
||||||
#endif /* CONFIG_USE_SEGGER_RTT */
|
#endif /* CONFIG_USE_SEGGER_RTT */
|
||||||
|
|
||||||
/* On some STM32 boards, for unclear reason,
|
/* On some STM32 boards, for unclear reason,
|
||||||
|
|
|
||||||
|
|
@ -13,5 +13,6 @@ config SOC_SERIES_STM32L5X
|
||||||
select ARMV8_M_DSP
|
select ARMV8_M_DSP
|
||||||
select CPU_CORTEX_M_HAS_DWT
|
select CPU_CORTEX_M_HAS_DWT
|
||||||
select HAS_STM32CUBE
|
select HAS_STM32CUBE
|
||||||
|
select HAS_SWO
|
||||||
select HAS_PM
|
select HAS_PM
|
||||||
select SOC_EARLY_INIT_HOOK
|
select SOC_EARLY_INIT_HOOK
|
||||||
|
|
|
||||||
|
|
@ -16,6 +16,7 @@ config SOC_SERIES_STM32U5X
|
||||||
select CPU_CORTEX_M_HAS_DWT
|
select CPU_CORTEX_M_HAS_DWT
|
||||||
select HAS_STM32CUBE
|
select HAS_STM32CUBE
|
||||||
select HAS_PM
|
select HAS_PM
|
||||||
|
select HAS_SWO
|
||||||
select HAS_POWEROFF
|
select HAS_POWEROFF
|
||||||
select SOC_EARLY_INIT_HOOK
|
select SOC_EARLY_INIT_HOOK
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue