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drivers: use fracn in clock stm32h7 driver

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use fracn value if defined for each PLL 1, 2 and 3 based on stm32u5 code

Signed-off-by: Nathan Olff <nathan@kickmaker.net>
This commit is contained in:
Nathan Olff 2024-08-22 23:28:33 +02:00 committed by Carles Cufí
parent 9dd25adc79
commit f979252cea
1 changed files with 12 additions and 1 deletions
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13
drivers/clock_control/clock_stm32_ll_h7.c
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@ -800,8 +800,11 @@ static int set_up_plls(void)
LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER); LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
/* FRACN disable DIVP,DIVQ,DIVR enable*/
LL_RCC_PLL1FRACN_Disable(); LL_RCC_PLL1FRACN_Disable();
if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {
LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE);
LL_RCC_PLL1FRACN_Enable();
}
if (IS_ENABLED(STM32_PLL_P_ENABLED)) { if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR); LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
@ -846,6 +849,10 @@ static int set_up_plls(void)
LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER); LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
LL_RCC_PLL2FRACN_Disable(); LL_RCC_PLL2FRACN_Disable();
if (IS_ENABLED(STM32_PLL2_FRACN_ENABLED)) {
LL_RCC_PLL2_SetFRACN(STM32_PLL2_FRACN_VALUE);
LL_RCC_PLL2FRACN_Enable();
}
if (IS_ENABLED(STM32_PLL2_P_ENABLED)) { if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {
LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR); LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR);
@ -896,6 +903,10 @@ static int set_up_plls(void)
LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER); LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
LL_RCC_PLL3FRACN_Disable(); LL_RCC_PLL3FRACN_Disable();
if (IS_ENABLED(STM32_PLL3_FRACN_ENABLED)) {
LL_RCC_PLL3_SetFRACN(STM32_PLL3_FRACN_VALUE);
LL_RCC_PLL3FRACN_Enable();
}
if (IS_ENABLED(STM32_PLL3_P_ENABLED)) { if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR); LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);