soc: arm: npcx: move soc-specific register definitions to soc.h
This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we introduce a new chip series. Most of them are relevant to register layouts in different npcx soc series. It moves soc-specific register definitions from `reg_def.h` to its own soc.h file. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao
Fabio Baltieri
parent
db0ec23ba4
commit
f9a4a3597b
7 changed files with 153 additions and 199 deletions
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@ -247,7 +247,6 @@ void qspi_npcx_fiu_mutex_unlock(const struct device *dev)
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static int qspi_npcx_fiu_init(const struct device *dev)
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{
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const struct npcx_qspi_fiu_config *const config = dev->config;
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struct fiu_reg *const inst = HAL_INSTANCE(dev);
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struct npcx_qspi_fiu_data *const data = dev->data;
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const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
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int ret;
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@ -270,9 +269,11 @@ static int qspi_npcx_fiu_init(const struct device *dev)
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/* Enable direct access for 2 external SPI devices */
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if (config->en_direct_access_2dev) {
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if (IS_ENABLED(CONFIG_FLASH_NPCX_FIU_SUPP_DRA_2_DEV)) {
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inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_SPI1_2DEV);
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}
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#if defined(CONFIG_FLASH_NPCX_FIU_SUPP_DRA_2_DEV)
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struct fiu_reg *const inst = HAL_INSTANCE(dev);
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inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_SPI1_2DEV);
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#endif
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}
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return 0;
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@ -38,17 +38,10 @@ static const struct npcx_pwm_pinctrl_config pwm_pinctrl_cfg[] = {
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/* Pin-control local functions for peripheral devices */
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static bool npcx_periph_pinmux_has_lock(int group)
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{
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#if defined(CONFIG_SOC_SERIES_NPCX7)
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if (group == 0x00 || (group >= 0x02 && group <= 0x04) || group == 0x06 ||
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group == 0x0b || group == 0x0f) {
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if ((BIT(group) & NPCX_DEVALT_LK_GROUP_MASK) != 0) {
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return true;
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}
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#elif defined(CONFIG_SOC_SERIES_NPCX9)
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if (group == 0x00 || (group >= 0x02 && group <= 0x06) || group == 0x0b ||
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group == 0x0d || (group >= 0x0f && group <= 0x12)) {
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return true;
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}
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#endif
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return false;
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}
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@ -228,49 +228,17 @@ struct scfg_reg {
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volatile uint8_t LV_GPIO_CTL0[5];
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};
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/* SCFG internal inline functions for multi-registers */
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static inline uint32_t npcx_devalt_offset(uint32_t alt_no)
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{
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return 0x010 + alt_no;
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}
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static inline uint32_t npcx_devalt_lk_offset(uint32_t alt_lk_no)
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{
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return 0x210 + alt_lk_no;
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}
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static inline uint32_t npcx_pupd_en_offset(uint32_t pupd_en_no)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
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return 0x28 + pupd_en_no;
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} else { /* NPCX4 and later series */
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return 0x2b + pupd_en_no;
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}
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}
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static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
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if (ctl_no < 5) {
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return 0x02a + ctl_no;
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} else {
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return 0x026 + ctl_no - 5;
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}
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} else { /* NPCX4 and later series */
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return 0x150 + ctl_no;
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}
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}
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/* Macro functions for SCFG multi-registers */
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#define NPCX_DEV_CTL(base, n) (*(volatile uint8_t *)(base + n))
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#define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + \
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npcx_devalt_offset(n)))
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#define NPCX_DEVALT_LK(base, n) (*(volatile uint8_t *)(base + \
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npcx_devalt_lk_offset(n)))
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#define NPCX_PUPD_EN(base, n) (*(volatile uint8_t *)(base + \
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npcx_pupd_en_offset(n)))
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#define NPCX_LV_GPIO_CTL(base, n) (*(volatile uint8_t *)(base + \
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npcx_lv_gpio_ctl_offset(n)))
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#define NPCX_DEV_CTL(base, n) \
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(*(volatile uint8_t *)(base + n))
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#define NPCX_DEVALT(base, n) \
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(*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
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#define NPCX_DEVALT_LK(base, n) \
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(*(volatile uint8_t *)(base + NPCX_DEVALT_LK_OFFSET(n)))
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#define NPCX_PUPD_EN(base, n) \
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(*(volatile uint8_t *)(base + NPCX_PUPD_EN_OFFSET(n)))
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#define NPCX_LV_GPIO_CTL(base, n) \
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(*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n)))
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/* SCFG register fields */
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#define NPCX_DEVCNT_F_SPI_TRIS 6
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@ -413,95 +381,21 @@ struct uart_reg {
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#define NPCX_UFRCTL_RNEMPTY_EN 6
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#define NPCX_UFRCTL_ERR_EN 7
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/*
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* Multi-Input Wake-Up Unit (MIWU) device registers
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*/
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/* MIWU internal inline functions for multi-registers */
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static inline uint32_t npcx_wkedg_offset(uint32_t group)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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return 0x000 + (group * 2ul) + (group < 5 ? 0 : 0x1e);
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} else { /* NPCX9 and later series */
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return 0x000 + group * 0x10UL;
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}
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}
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static inline uint32_t npcx_wkaedg_offset(uint32_t group)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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return 0x001 + (group * 2ul) + (group < 5 ? 0 : 0x1e);
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} else { /* NPCX9 and later series */
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return 0x001 + group * 0x10ul;
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}
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}
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static inline uint32_t npcx_wkmod_offset(uint32_t group)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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return 0x070 + group;
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} else { /* NPCX9 and later series */
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return 0x002 + group * 0x10ul;
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}
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}
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static inline uint32_t npcx_wkpnd_offset(uint32_t group)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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return 0x00a + (group * 4ul) + (group < 5 ? 0 : 0x10);
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} else { /* NPCX9 and later series */
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return 0x003 + group * 0x10ul;
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}
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}
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static inline uint32_t npcx_wkpcl_offset(uint32_t group)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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return 0x00c + (group * 4ul) + (group < 5 ? 0 : 0x10);
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} else { /* NPCX9 and later series */
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return 0x004 + group * 0x10ul;
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}
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}
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static inline uint32_t npcx_wken_offset(uint32_t group)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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return 0x01e + (group * 2ul) + (group < 5 ? 0 : 0x12);
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} else { /* NPCX9 and later series */
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return 0x005 + group * 0x10ul;
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}
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}
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static inline uint32_t npcx_wkst_offset(uint32_t group)
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{
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/* NPCX9 and later series only */
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return 0x006 + group * 0x10ul;
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}
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static inline uint32_t npcx_wkinen_offset(uint32_t group)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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return 0x01f + (group * 2ul) + (group < 5 ? 0 : 0x12);
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} else { /* NPCX9 and later series */
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return 0x007 + group * 0x10ul;
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}
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}
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/* Macro functions for MIWU multi-registers */
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#define NPCX_WKEDG(base, group) \
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(*(volatile uint8_t *)(base + npcx_wkedg_offset(group)))
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(*(volatile uint8_t *)(base + NPCX_WKEDG_OFFSET(group)))
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#define NPCX_WKAEDG(base, group) \
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(*(volatile uint8_t *)(base + npcx_wkaedg_offset(group)))
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(*(volatile uint8_t *)(base + NPCX_WKAEDG_OFFSET(group)))
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#define NPCX_WKPND(base, group) \
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(*(volatile uint8_t *)(base + npcx_wkpnd_offset(group)))
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(*(volatile uint8_t *)(base + NPCX_WKPND_OFFSET(group)))
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#define NPCX_WKPCL(base, group) \
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(*(volatile uint8_t *)(base + npcx_wkpcl_offset(group)))
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(*(volatile uint8_t *)(base + NPCX_WKPCL_OFFSET(group)))
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#define NPCX_WKEN(base, group) \
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(*(volatile uint8_t *)(base + npcx_wken_offset(group)))
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(*(volatile uint8_t *)(base + NPCX_WKEN_OFFSET(group)))
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#define NPCX_WKINEN(base, group) \
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(*(volatile uint8_t *)(base + npcx_wkinen_offset(group)))
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(*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group)))
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#define NPCX_WKMOD(base, group) \
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(*(volatile uint8_t *)(base + npcx_wkmod_offset(group)))
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(*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group)))
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/*
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* General-Purpose I/O (GPIO) device registers
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@ -582,33 +476,10 @@ struct adc_reg {
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};
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/* ADC internal inline functions for multi-registers */
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static inline uint32_t npcx_chndat_offset(uint32_t ch)
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{
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return 0x40 + ch * 2;
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}
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static inline uint32_t npcx_thr_base(void)
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{
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
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return 0x014;
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} else if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
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return 0x060;
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} else { /* NPCX4 and later series */
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return 0x080;
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}
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}
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static inline uint32_t npcx_thrctl_offset(uint32_t ctrl)
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{
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return npcx_thr_base() + ctrl * 2;
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}
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#define CHNDAT(base, ch) (*(volatile uint16_t *)((base) + npcx_chndat_offset(ch)))
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#define CHNDAT(base, ch) \
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(*(volatile uint16_t *)((base) + NPCX_CHNDAT_OFFSET(ch)))
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#define THRCTL(base, ctrl) \
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(*(volatile uint16_t *)(base + npcx_thrctl_offset(ctrl)))
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#ifdef CONFIG_SOC_SERIES_NPCX4
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#define THEN(base) (*(volatile uint16_t *)(base + 0x90))
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#endif
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(*(volatile uint16_t *)(base + NPCX_THRCTL_OFFSET(ctrl)))
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/* ADC register fields */
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#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
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@ -628,16 +499,6 @@ static inline uint32_t npcx_thrctl_offset(uint32_t ctrl)
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#define NPCX_ADCCNF_STOP 11
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#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
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#define NPCX_CHNDAT_NEW 15
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#ifdef CONFIG_SOC_SERIES_NPCX4
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#define NPCX_THRCTL_L_H 15
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#define NPCX_THRCTL_CHNSEL FIELD(10, 5)
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#define NPCX_THRCTL_THRVAL FIELD(0, 10)
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#else
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#define NPCX_THRCTL_THEN 15
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#define NPCX_THRCTL_L_H 14
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#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
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#define NPCX_THRCTL_THRVAL FIELD(0, 10)
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#endif
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#define NPCX_THRCTS_ADC_WKEN 15
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#define NPCX_THRCTS_THR3_IEN 10
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#define NPCX_THRCTS_THR2_IEN 9
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@ -1598,11 +1459,6 @@ struct fiu_reg {
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#define NPCX_SPI1_DEV_FOUR_BADDR_CS10 6
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#define NPCX_SPI1_DEV_FOUR_BADDR_CS11 7
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#define NPCX_SPI1_DEV_SPI1_LO_DEV_SIZE FIELD(0, 4)
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#if defined(CONFIG_SOC_SERIES_NPCX9)
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#define NPCX_FIU_EXT_CFG_SPI1_2DEV 7
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#else
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#define NPCX_FIU_EXT_CFG_SPI1_2DEV 6
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#endif
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#define NPCX_FIU_EXT_CFG_SET_DMM_EN 2
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#define NPCX_FIU_EXT_CFG_SET_CMD_EN 1
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#define NPCX_SPI_DEV_NADDRB FIELD(5, 3)
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@ -42,14 +42,6 @@ struct npcx_clk_cfg {
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#define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
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/* APB3 clock divider */
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#define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
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/* APB4 clock divider if supported */
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
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#if !defined(CONFIG_SOC_SERIES_NPCX7) /* Supported in NPCX9 and later series */
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#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
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#else
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#error "APB4 clock divider is not supported but defined in pcc node!"
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#endif /* !CONFIG_SOC_SERIES_NPCX7 */
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#endif
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/* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
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#define NPCX_PWDWN_CTL_ITEMS_INIT(node, prop, idx) DT_PROP_BY_IDX(node, prop, idx),
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@ -68,12 +60,6 @@ struct npcx_clk_cfg {
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* - CORE_CLK > MAX_OFMCLK/2, AHB6DIV should be 1, else 0.
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* - CORE_CLK > MAX_OFMCLK/2, FIUDIV should be 1, else 0.
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*/
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#if defined(CONFIG_SOC_SERIES_NPCX4)
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#define MAX_OFMCLK 120000000
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#else
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#define MAX_OFMCLK 100000000
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#endif /* CONFIG_SOC_SERIES_NPCX4 */
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/* Core domain clock */
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#define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
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/* Low Frequency clock */
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@ -103,14 +89,6 @@ struct npcx_clk_cfg {
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#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
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#endif
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#if defined(CONFIG_SOC_SERIES_NPCX4)
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#if (CORE_CLK > (MAX_OFMCLK / 2))
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#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
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#else
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#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
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#endif
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#endif /* CONFIG_SOC_SERIES_NPCX4 */
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/* Get APB clock freq */
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#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
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@ -11,6 +11,45 @@
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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/* NPCX4 SCFG multi-registers */
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#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
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#define NPCX_PUPD_EN_OFFSET(n) (0x02b + n)
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#define NPCX_LV_GPIO_CTL_OFFSET(n) (0x150 + n)
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#define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n)
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/* NPCX4 MIWU multi-registers */
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#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010))
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#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010))
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#define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010))
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#define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010))
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#define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010))
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#define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010))
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#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
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#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
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/* NPCX4 ADC multi-registers */
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#define NPCX_CHNDAT_OFFSET(n) (0x040 + n * 2)
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#define NPCX_THRCTL_OFFSET(n) (0x080 + n * 2)
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#define NPCX_THEN_OFFSET 0x090
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#define THEN(base) (*(volatile uint16_t *)(base + NPCX_THEN_OFFSET))
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/* NPCX4 ADC register fields */
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#define NPCX_THRCTL_L_H 15
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#define NPCX_THRCTL_CHNSEL FIELD(10, 5)
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#define NPCX_THRCTL_THRVAL FIELD(0, 10)
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/* NPCX4 FIU register fields */
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#define NPCX_FIU_EXT_CFG_SPI1_2DEV 6
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/* NPCX4 supported group mask of DEVALT_LK */
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#define NPCX_DEVALT_LK_GROUP_MASK \
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(BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
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BIT(5) | BIT(6) | BIT(11) | BIT(13) | \
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BIT(15) | BIT(16) | BIT(17) | BIT(18) | \
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BIT(19) | BIT(21)) /* DEVALT0_LK - DEVALTN_LK */
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/* NPCX4 Clock Configuration */
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#define MAX_OFMCLK 120000000
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#include <reg/reg_access.h>
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#include <reg/reg_def.h>
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@ -19,4 +58,16 @@
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#include <soc_pins.h>
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#include <soc_power.h>
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/* NPCX4 Clock definitions */
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
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/* APB4 clock divider if supported */
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#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
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#endif
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#if (CORE_CLK > (MAX_OFMCLK / 2))
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#define FIU1DIV_VAL 1 /* If CORE_CLK > MAX_OFMCLK / 2, FIU1_CLK = CORE_CLK/2 */
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#else
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#define FIU1DIV_VAL 0 /* Else, FIU1_CLK = CORE_CLK */
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#endif
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#endif /* _NUVOTON_NPCX_SOC_H_ */
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@ -11,6 +11,38 @@
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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/* NPCX7 SCFG multi-registers offset */
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#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
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#define NPCX_PUPD_EN_OFFSET(n) (0x028 + n)
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#define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n))
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#define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n)
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/* NPCX7 MIWU multi-registers offset */
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#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 2) + ((n < 5) ? 0 : 0x01e))
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#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 2) + ((n < 5) ? 0 : 0x01e))
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#define NPCX_WKMOD_OFFSET(n) (0x070 + n)
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#define NPCX_WKPND_OFFSET(n) (0x00a + (n * 4) + ((n < 5) ? 0 : 0x010))
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#define NPCX_WKPCL_OFFSET(n) (0x00c + (n * 4) + ((n < 5) ? 0 : 0x010))
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#define NPCX_WKEN_OFFSET(n) (0x01e + (n * 2) + ((n < 5) ? 0 : 0x012))
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#define NPCX_WKINEN_OFFSET(n) (0x01f + (n * 2) + ((n < 5) ? 0 : 0x012))
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/* NPCX7 ADC multi-registers offset */
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||||
#define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2))
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#define NPCX_THRCTL_OFFSET(n) (0x014 + (n * 2))
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||||
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||||
/* NPCX7 ADC register fields */
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||||
#define NPCX_THRCTL_THEN 15
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||||
#define NPCX_THRCTL_L_H 14
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||||
#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
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||||
#define NPCX_THRCTL_THRVAL FIELD(0, 10)
|
||||
|
||||
/* NPCX7 supported group mask of DEVALT_LK */
|
||||
#define NPCX_DEVALT_LK_GROUP_MASK \
|
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(BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
|
||||
BIT(6) | BIT(11) | BIT(15)) /* DEVALT0_LK - DEVALTF_LK */
|
||||
|
||||
/* NPCX7 Clock configuration */
|
||||
#define MAX_OFMCLK 100000000
|
||||
|
||||
#include <reg/reg_access.h>
|
||||
#include <reg/reg_def.h>
|
||||
|
|
|
|||
|
|
@ -11,6 +11,43 @@
|
|||
#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
|
||||
#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
|
||||
|
||||
/* NPCX9 SCFG multi-registers */
|
||||
#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
|
||||
#define NPCX_PUPD_EN_OFFSET(n) (0x028 + n)
|
||||
#define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n))
|
||||
#define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n)
|
||||
|
||||
/* NPCX9 MIWU multi-registers */
|
||||
#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010))
|
||||
#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010))
|
||||
#define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010))
|
||||
#define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010))
|
||||
#define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010))
|
||||
#define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010))
|
||||
#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
|
||||
#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
|
||||
|
||||
/* NPCX9 ADC multi-registers */
|
||||
#define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2))
|
||||
#define NPCX_THRCTL_OFFSET(n) (0x060 + (n * 2))
|
||||
|
||||
/* NPCX9 ADC register fields */
|
||||
#define NPCX_THRCTL_THEN 15
|
||||
#define NPCX_THRCTL_L_H 14
|
||||
#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
|
||||
#define NPCX_THRCTL_THRVAL FIELD(0, 10)
|
||||
|
||||
/* NPCX9 FIU register fields */
|
||||
#define NPCX_FIU_EXT_CFG_SPI1_2DEV 7
|
||||
|
||||
/* NPCX9 supported group mask of DEVALT_LK */
|
||||
#define NPCX_DEVALT_LK_GROUP_MASK \
|
||||
(BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
|
||||
BIT(5) | BIT(6) | BIT(11) | BIT(13) | \
|
||||
BIT(15) | BIT(16) | BIT(17) | BIT(18)) /* DEVALT0_LK - DEVALTJ_LK */
|
||||
|
||||
/* NPCX9 Clock configuration and limitation */
|
||||
#define MAX_OFMCLK 100000000
|
||||
|
||||
#include <reg/reg_access.h>
|
||||
#include <reg/reg_def.h>
|
||||
|
|
@ -19,4 +56,10 @@
|
|||
#include <soc_pins.h>
|
||||
#include <soc_power.h>
|
||||
|
||||
/* NPCX9 Clock definitions */
|
||||
#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
|
||||
/* APB4 clock divider if supported */
|
||||
#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
|
||||
#endif
|
||||
|
||||
#endif /* _NUVOTON_NPCX_SOC_H_ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue