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soc: st: stm32: stm32g0x: enable ART flash cache accelerator

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Enable instruction cache and prefetching on STM32G0X SoC family.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2024-05-18 08:28:24 +02:00 committed by Anas Nashif
parent 858e8c51f1
commit fac04490a4
1 changed files with 5 additions and 1 deletions
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6
soc/st/stm32/stm32g0x/soc.c
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@ -16,8 +16,8 @@
#include <string.h>
#include <cmsis_core.h>
#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
#include <stm32_ll_system.h>
#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
#include <stm32_ll_bus.h>
#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
@ -81,6 +81,10 @@ static void stm32g0_disable_dead_battery(void)
*/
static int stm32g0_init(void)
{
/* Enable ART Accelerator I-cache and prefetch */
LL_FLASH_EnableInstCache();
LL_FLASH_EnablePrefetch();
/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 16 MHz from HSI */
SystemCoreClock = 16000000;