drivers: flash: add NXP S32 QSPI HyperFlash driver
Add support HyperFlash memory devices on a NXP S32 QSPI bus. This driver uses a fixed LUT configuration that defined in HAL RTD HyperFlash driver. Driver allows to read, write and erase HyperFlash devices. Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
This commit is contained in:
Cong Nguyen Huu
Benjamin Cabé
parent
f0c4d1c53c
commit
fd620c3ef9
4 changed files with 367 additions and 8 deletions
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@ -149,11 +149,11 @@ zephyr_library_include_directories_ifdef(
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)
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zephyr_library_sources_ifdef(CONFIG_FLASH_NXP_S32_QSPI_NOR flash_nxp_s32_qspi_nor.c)
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zephyr_library_sources_ifdef(CONFIG_FLASH_NXP_S32_QSPI_NOR flash_nxp_s32_qspi.c)
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zephyr_library_include_directories_ifdef(
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CONFIG_FLASH_NXP_S32_QSPI_NOR
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${ZEPHYR_BASE}/drivers/memc
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)
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zephyr_library_sources_ifdef(CONFIG_FLASH_NXP_S32_QSPI_HYPERFLASH flash_nxp_s32_qspi_hyperflash.c)
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if(CONFIG_FLASH_NXP_S32_QSPI_NOR OR CONFIG_FLASH_NXP_S32_QSPI_HYPERFLASH)
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zephyr_library_sources(flash_nxp_s32_qspi.c)
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc)
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endif()
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if(CONFIG_RA_FLASH_HP)
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zephyr_library_sources(flash_hp_ra.c)
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@ -1,4 +1,4 @@
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# Copyright 2023 NXP
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# Copyright 2023-2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config FLASH_NXP_S32_QSPI_NOR
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@ -14,10 +14,23 @@ config FLASH_NXP_S32_QSPI_NOR
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Enable the Flash driver for a NOR Serial Flash Memory device connected
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to an NXP S32 QSPI bus.
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if FLASH_NXP_S32_QSPI_NOR
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config FLASH_NXP_S32_QSPI_HYPERFLASH
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bool "NXP S32 QSPI HYPERFLASH driver"
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default y
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depends on DT_HAS_NXP_S32_QSPI_HYPERFLASH_ENABLED
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select MEMC
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select FLASH_HAS_PAGE_LAYOUT
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select FLASH_HAS_DRIVER_ENABLED
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select FLASH_HAS_EXPLICIT_ERASE
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help
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Enable the Flash driver for a HyperFlash Memory device connected
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to an NXP S32 QSPI bus.
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if FLASH_NXP_S32_QSPI_NOR || FLASH_NXP_S32_QSPI_HYPERFLASH
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config FLASH_NXP_S32_QSPI_SFDP_RUNTIME
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bool "Read flash parameters at runtime"
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depends on FLASH_NXP_S32_QSPI_NOR
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help
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Read flash device characteristics from the device at runtime.
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This option should provide functionality for all supported
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@ -52,4 +65,4 @@ config FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE
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flash memory. Other options may include the 32K-byte erase size (32768),
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the block size (65536), or any non-zero multiple of the sector size.
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endif # FLASH_NXP_S32_QSPI_NOR
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endif # FLASH_NXP_S32_QSPI_NOR || FLASH_NXP_S32_QSPI_HYPERFLASH
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247
drivers/flash/flash_nxp_s32_qspi_hyperflash.c
Normal file
247
drivers/flash/flash_nxp_s32_qspi_hyperflash.c
Normal file
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@ -0,0 +1,247 @@
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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_s32_qspi_hyperflash
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/flash.h>
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#include <zephyr/logging/log.h>
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#include <Qspi_Ip.h>
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#include "memc_nxp_s32_qspi.h"
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#include "flash_nxp_s32_qspi.h"
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LOG_MODULE_REGISTER(nxp_s32_qspi_hyperflash, CONFIG_FLASH_LOG_LEVEL);
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/* Use the fixed command sets from Qspi_Ip_Hyperflash.c */
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extern Qspi_Ip_InstrOpType QSPI_IP_HF_LUT_NAME[QSPI_IP_HF_LUT_SIZE];
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static int nxp_s32_qspi_init(const struct device *dev)
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{
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struct nxp_s32_qspi_data *data = dev->data;
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const struct nxp_s32_qspi_config *config = dev->config;
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Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
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uint8_t dev_id[memory_cfg->readIdSettings.readIdSize];
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Qspi_Ip_StatusType status;
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int ret = 0;
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/* Used by the HAL to retrieve the internal driver state */
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data->instance = nxp_s32_qspi_register_device();
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__ASSERT_NO_MSG(data->instance < QSPI_IP_MEM_INSTANCE_COUNT);
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data->memory_conn_cfg.qspiInstance = memc_nxp_s32_qspi_get_instance(config->controller);
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#if defined(CONFIG_MULTITHREADING)
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k_sem_init(&data->sem, 1, 1);
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#endif
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if (!device_is_ready(config->controller)) {
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LOG_ERR("Memory control device not ready");
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return -ENODEV;
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}
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status = Qspi_Ip_Init(data->instance, (const Qspi_Ip_MemoryConfigType *)memory_cfg,
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(const Qspi_Ip_MemoryConnectionType *)&data->memory_conn_cfg);
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if (status != STATUS_QSPI_IP_SUCCESS) {
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LOG_ERR("Fail to init memory device %d (%d)", data->instance, status);
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return -EIO;
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}
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/* Verify connectivity by reading the device ID */
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ret = nxp_s32_qspi_read_id(dev, dev_id);
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if (ret != 0) {
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LOG_ERR("Device ID read failed (%d)", ret);
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return -ENODEV;
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}
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if (memcmp(dev_id, memory_cfg->readIdSettings.readIdExpected, sizeof(dev_id))) {
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LOG_ERR("Device id does not match config");
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return -EINVAL;
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}
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return ret;
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}
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static DEVICE_API(flash, nxp_s32_qspi_api) = {
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.erase = nxp_s32_qspi_erase,
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.write = nxp_s32_qspi_write,
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.read = nxp_s32_qspi_read,
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.get_parameters = nxp_s32_qspi_get_parameters,
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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.page_layout = nxp_s32_qspi_pages_layout,
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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};
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#define QSPI_PAGE_LAYOUT(n) \
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.layout = { \
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.pages_count = (DT_INST_PROP(n, size) / 8) \
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/ CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE, \
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.pages_size = CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE, \
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}
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#define QSPI_READ_ID_CFG(n) \
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{ \
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.readIdLut = QSPI_IP_HF_LUT_READ, \
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.readIdSize = DT_INST_PROP_LEN(n, jedec_id), \
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.readIdExpected = DT_INST_PROP(n, jedec_id), \
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}
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#define QSPI_MEMORY_CONN_CFG(n) \
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{ \
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.connectionType = (Qspi_Ip_ConnectionType)DT_INST_REG_ADDR(n), \
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.memAlignment = DT_INST_PROP(n, write_block_size) \
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}
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#define QSPI_ERASE_CFG(n) \
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{ \
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.eraseTypes = { \
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{ \
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.eraseLut = QSPI_IP_HF_LUT_SE, \
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.size = 12, /* 4 KB */ \
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}, \
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{ \
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.eraseLut = QSPI_IP_HF_LUT_SE, \
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.size = 18, /* 256 KB */ \
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}, \
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{ \
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.eraseLut = QSPI_IP_LUT_INVALID, \
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.size = 0, \
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}, \
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{ \
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.eraseLut = QSPI_IP_LUT_INVALID, \
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.size = 0, \
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}, \
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}, \
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.chipEraseLut = QSPI_IP_HF_LUT_CE, \
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}
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#define QSPI_RESET_CFG(n) \
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{ \
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.resetCmdLut = QSPI_IP_HF_LUT_RST, \
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.resetCmdCount = QSPI_IP_HF_RST_CNT, \
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}
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#define QSPI_STATUS_REG_CFG(n) \
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{ \
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.statusRegInitReadLut = QSPI_IP_HF_LUT_RDSR, \
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.statusRegReadLut = QSPI_IP_HF_LUT_RDSR, \
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.statusRegWriteLut = QSPI_IP_LUT_INVALID, \
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.writeEnableSRLut = QSPI_IP_LUT_INVALID, \
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.writeEnableLut = QSPI_IP_LUT_INVALID, \
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.regSize = 1U, \
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.busyOffset = 0U, \
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.busyValue = 1U, \
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.writeEnableOffset = 1U, \
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}
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#define QSPI_INIT_CFG(n) \
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{ \
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.opCount = 0U, \
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.operations = NULL, \
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}
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#define QSPI_LUT_CFG(n) \
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{ \
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.opCount = QSPI_IP_HF_LUT_SIZE, \
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.lutOps = (Qspi_Ip_InstrOpType *)QSPI_IP_HF_LUT_NAME, \
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}
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#define QSPI_SUSPEND_CFG(n) \
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{ \
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.eraseSuspendLut = QSPI_IP_HF_LUT_ES, \
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.eraseResumeLut = QSPI_IP_HF_LUT_ER, \
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.programSuspendLut = QSPI_IP_HF_LUT_PS, \
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.programResumeLut = QSPI_IP_HF_LUT_PR, \
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}
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#define QSPI_MEMORY_CFG(n) \
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{ \
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.memType = QSPI_IP_HYPER_FLASH, \
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.hfConfig = &hyperflash_config_##n, \
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.memSize = DT_INST_PROP(n, size) / 8, \
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.pageSize = DT_INST_PROP(n, max_program_buffer_size), \
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.writeLut = QSPI_IP_HF_LUT_WRITE, \
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.readLut = QSPI_IP_HF_LUT_READ, \
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.read0xxLut = QSPI_IP_LUT_INVALID, \
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.read0xxLutAHB = QSPI_IP_LUT_INVALID, \
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.eraseSettings = QSPI_ERASE_CFG(n), \
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.statusConfig = QSPI_STATUS_REG_CFG(n), \
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.resetSettings = QSPI_RESET_CFG(n), \
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.initResetSettings = QSPI_RESET_CFG(n), \
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.initConfiguration = QSPI_INIT_CFG(n), \
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.lutSequences = QSPI_LUT_CFG(n), \
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.readIdSettings = QSPI_READ_ID_CFG(n), \
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.suspendSettings = QSPI_SUSPEND_CFG(n), \
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.initCallout = NULL, \
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.resetCallout = NULL, \
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.errorCheckCallout = NULL, \
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.eccCheckCallout = NULL, \
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.ctrlAutoCfgPtr = NULL, \
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}
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#define FLASH_NXP_S32_QSPI_DRV_STRENGTH(n) \
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COND_CODE_1(DT_INST_ENUM_IDX(n, vcc_mv), \
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(DT_INST_PROP(n, drive_strength_ohm) == 12 ? QSPI_IP_HF_DRV_STRENGTH_007 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 14 ? QSPI_IP_HF_DRV_STRENGTH_006 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 16 ? QSPI_IP_HF_DRV_STRENGTH_005 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 20 ? QSPI_IP_HF_DRV_STRENGTH_000 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 27 ? QSPI_IP_HF_DRV_STRENGTH_003 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 40 ? QSPI_IP_HF_DRV_STRENGTH_002 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 71 ? QSPI_IP_HF_DRV_STRENGTH_001 : \
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QSPI_IP_HF_DRV_STRENGTH_000))))))), \
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(DT_INST_PROP(n, drive_strength_ohm) == 20 ? QSPI_IP_HF_DRV_STRENGTH_007 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 24 ? QSPI_IP_HF_DRV_STRENGTH_006 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 27 ? QSPI_IP_HF_DRV_STRENGTH_000 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 34 ? QSPI_IP_HF_DRV_STRENGTH_004 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 45 ? QSPI_IP_HF_DRV_STRENGTH_003 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 68 ? QSPI_IP_HF_DRV_STRENGTH_002 : \
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(DT_INST_PROP(n, drive_strength_ohm) == 117 ? QSPI_IP_HF_DRV_STRENGTH_001 : \
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QSPI_IP_HF_DRV_STRENGTH_000))))))))
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#define FLASH_NXP_S32_QSPI_SECTOR_MAP(n) \
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COND_CODE_1(DT_INST_PROP(n, support_only_uniform_sectors), \
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(DT_INST_ENUM_IDX(n, ppw_sectors_addr_mapping) ? \
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QSPI_IP_HF_UNIFORM_SECTORS_READ_PASSWORD_HIGH : \
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QSPI_IP_HF_UNIFORM_SECTORS_READ_PASSWORD_LOW), \
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(DT_INST_ENUM_IDX(n, ppw_sectors_addr_mapping) ? \
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QSPI_IP_HF_PARAM_AND_PASSWORD_MAP_HIGH : \
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QSPI_IP_HF_PARAM_AND_PASSWORD_MAP_LOW))
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#define FLASH_NXP_S32_QSPI_INIT_DEVICE(n) \
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static Qspi_Ip_HyperFlashConfigType hyperflash_config_##n = \
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{ \
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.outputDriverStrength = FLASH_NXP_S32_QSPI_DRV_STRENGTH(n), \
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.RWDSLowOnDualError = DT_INST_PROP(n, rwds_low_dual_error), \
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.secureRegionUnlocked = !DT_INST_PROP(n, secure_region_locked), \
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.readLatency = DT_INST_ENUM_IDX(n, read_latency_cycles), \
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.paramSectorMap = FLASH_NXP_S32_QSPI_SECTOR_MAP(n), \
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.deviceIdWordAddress = DT_INST_PROP(n, device_id_word_addr), \
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}; \
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static const struct nxp_s32_qspi_config nxp_s32_qspi_config_##n = { \
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.controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
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.flash_parameters = { \
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.write_block_size = DT_INST_PROP(n, write_block_size), \
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.erase_value = QSPI_ERASE_VALUE, \
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}, \
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IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, \
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(QSPI_PAGE_LAYOUT(n),)) \
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.memory_cfg = QSPI_MEMORY_CFG(n), \
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}; \
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\
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static struct nxp_s32_qspi_data nxp_s32_qspi_data_##n = { \
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.memory_conn_cfg = QSPI_MEMORY_CONN_CFG(n), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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nxp_s32_qspi_init, \
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NULL, \
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&nxp_s32_qspi_data_##n, \
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&nxp_s32_qspi_config_##n, \
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POST_KERNEL, \
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CONFIG_FLASH_INIT_PRIORITY, \
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&nxp_s32_qspi_api);
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DT_INST_FOREACH_STATUS_OKAY(FLASH_NXP_S32_QSPI_INIT_DEVICE)
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99
dts/bindings/mtd/nxp,s32-qspi-hyperflash.yaml
Normal file
99
dts/bindings/mtd/nxp,s32-qspi-hyperflash.yaml
Normal file
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@ -0,0 +1,99 @@
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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QSPI hyperflash connected to the NXP S32 QSPI bus.
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compatible: "nxp,s32-qspi-hyperflash"
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include: "nxp,s32-qspi-device.yaml"
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properties:
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device-id-word-addr:
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required: true
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type: int
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description: |
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The word address of the device ID in ASO (Application-Specific Object).
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This address specifies the exact location within the memory where the device ID is stored.
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rwds-low-dual-error:
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type: boolean
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description: |
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Enable Read-Write Data Strobe (RWDS) dual error detect.
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secure-region-locked:
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type: boolean
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description: |
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The secure region is locked and cannot be accessed or modified.
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This is particularly useful in scenarios where sensitive data needs protection from
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unauthorized access, such as in financial applications or secure communication systems.
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If it is disable, having access to all memory regions is beneficial during development
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or debugging phases.
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vcc-mv:
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type: int
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required: true
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enum:
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- 1800
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- 3000
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description: |
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The memory operating voltage supply in mV.
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drive-strength-ohm:
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type: int
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required: true
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enum:
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- 12
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- 14
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- 16
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- 20
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- 24
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- 27
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- 34
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- 40
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- 45
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- 68
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- 71
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- 117
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description: |
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Specifies the output drive strength in ohm, which based on the operating device VCC.
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The supported typical impedance settings:
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For 1.8V: 117 Ohm, 68 Ohm, 45 Ohm, 34 Ohm, 27 Ohm, 24 Ohm, 20 Ohm
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For 3V: 71 Ohm, 40 Ohm, 27 Ohm, 20 Ohm, 16 Ohm, 14 Ohm, 12 Ohm
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See the xVCR[14:12] field in VCR configuration register in the memory device datasheet.
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read-latency-cycles:
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type: int
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required: true
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enum:
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- 5
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- 6
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- 7
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- 8
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- 9
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- 10
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- 11
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- 12
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- 13
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- 14
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- 15
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- 16
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description: |
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Specifies the read latency in cycles, which is determined based on the operating frequency
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as specified in the memory device datasheet.
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support-only-uniform-sectors:
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type: boolean
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description: |
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The memory device supports only uniform (256KB) sectors.
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ppw-sectors-addr-mapping:
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type: string
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||||
required: true
|
||||
enum:
|
||||
- LOW
|
||||
- HIGH
|
||||
description: |
|
||||
The mapping of the parameter and read password sectors:
|
||||
- LOW: Parameter and read password sectors mapped into lowest addresses
|
||||
- HIGH: Parameter and read password sectors mapped into highest addresses
|
||||
Loading…
Reference in a new issue