Check that the stack frame pointer is valid before dumping
any registers while handling exceptions. If the pointer is
invalid, anything it points to will probably be also be
invalid. Accessing them may result in another access
violation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
It is observed that during logging in fatal exception,
it prints "FATAL EXCEPTION(null)". Exact reason is unknown
as debugging through GDB would make it all work again. So
separating it into two log statements to avoid this situation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When CONFIG_X86_EXCEPTION_STACK_TRACE is enabled, also forcibly
enable CONFIG_THREAD_STACK_INFO. Without the thread stack info,
it is possible the stack unwinding would go out of the thread
stack and into unknown memory, resulting in hard fault.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There actually is no triple faults on Xtensa. Once PS.EXCM is
set, it keeps going through double exception vector for any
new exceptions. However, our exception code needs to unmask
PS.EXCM to enable register window operations. So after that,
any new exceptions will go through the kernel or user vectors
depending on PS.UM. If there is continuous faults, it may
keep ping-ponging between double and kernel/user exception
vectors that may never get resolved. Since we stash DEPC
during double exception, and the stashed one is only cleared
once the double exception has been processed, we can use
the stashed DEPC value to detect if the next exception could
be considered a triple fault. If such a case exists, simply
jump to an infinite loop, or quit the simulator, or invoke
debugger.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_user_string_nlen() did not exactly work correctly as any
invalid pointers being passed are de-referenced naively, which
results in DTLB misses (MMU) or access errors (MPU). However,
arch_user_string_nlen() should always return to the caller
with appropriate error code set, and should never result in
thread termination. Since we are usually going through syscalls
when arch_user_string_nlen() is called, for MMU, the DTLB miss
goes through double exception. Since the pointer is invalid,
there is a high chance there is not even a L2 page table
associated with that bad address. So the DTLB miss cannot be
handled and it just keeps looping in double exception until
there is another exception type where we get to the C handler.
However, the stack frame is no longer the frame associated
with the call to arch_user_string_nlen(), and the call return
address would be incorrect. Forcing this incorrect address as
the next PC would result in some other exceptions, e.g.
illegal instruction, which would go to the C handler again.
This time it will go to the end of handler and would result
in thread termination. For MPU systems, access errors would
simply result in thread terminal in the C handler. Because of
these reasons, change the arch_user_string_nlen() to check if
the memory region can be accessed under kernel mode first
before feeding it to strnlen().
Also remove the exception fixup arrays as there is nothing
there anymore.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a new function xtensa_mem_kernel_has_access() to
determine if a memory region can be accessed by kernel threads.
This allows checking for valid mapped memory before accessing
them to avoid relying on page faults to detect invalid access.
Also fixed an issue with arch_buffer_validate() on MPU where
it may return okay even if the incoming memory region has no
corresponding entry in the MPU table.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_buffer_validate() is only to verify that user threads have
access to the memory region. It should not be used to verify
if kernel thread has access (which they should anyway). So
change the logic.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Introduce CONFIG_XTENSA_BREAK_ON_UNRECOVERABLE_EXCEPTIONS to
use BREAK instruction for unrecoverable exceptions. This
definitely requires debugger to be attached to the hardware
or simulator to catch that.
Also move the infinite loop to NOT result in an infinite
interrupt storm as the debug interrupt will be triggered over
and over again. Same for the simcall exit as it does not
need to be called repetitively.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If there are any TLB misses during interrupt handling,
the user, kernel and double exception vector will be triggered
for the miss and the DEPC and EXCCAUSE overwritten as the TLB
missse are be handled in the assembly code and execution
returned to the original vector code. Because of this, both
DEPC and EXCCAUSE being read in the C handler are not the ones
that triggered the original exception (for example, level-1
interrupt). So stash both DEPC and EXCCAUSE such that
the original cause of exception is visible in the C handler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Xtensa MPU code does not handle double exception in C. So there
is no need to clear DEPC on C handler exit.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
We have frame pointer struct and BSA struct to extract
the exception cause (exccause). There is no need to
resort to custom assembly to do that. Besides, given
that the BSA is different between different Xtensa cores,
there is no guarantee it is at the same place as what
the assembly assumes. So just do that without assembly.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Kconfig, .ld and comments fixing
Fixed address of UART1, WDT and RTC timer disabled by default
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Assembly implementation for z_early_memset() and z_early_memcpy().
Otherwise the compiler will happily replace our C code with a direct
call to memset/memcpy which kind of defeats the purpose.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
We need those simple alternatives to be used during early boot when the
MMU is not yet enabled. However they don't have to be the slowest they
can be. Those functions are mainly used to clear .bss sections and copy
.data to final destination when doing XIP, etc. Therefore it is very
likely for provided pointers to be 64-bit aligned. Let's optimize for
that case.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
As we start to use data memory barriers in SMP scheduler code
explicitly (not only internaly in the atomics implementation)
let's enable barriers for ARC HS.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Check if an address is in the thread stack only when
`CONFIG_THREAD_STACK_INFO` is enabled, since otherwise the
`stack_info` will not be available.
This fixes compilation error when `CONFIG_THREAD_STACK_INFO`
is explicitly disabled.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Many boards/SoCs in-tree do this:
if !XIP
config FLASH_SIZE
default 0
config FLASH_BASE_ADDRESS
default 0
endif
And many other boards are missing this configuration (e.g. stm32 series).
Making this the default helps get non-XIP just working
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Commit f7e11649fd ("arch/arm64/mmu: fix page table reference
counting") missed a case where the freeing of a table wasn't propagated
properly to all domains. To fix this, the page freeing logic was removed
from set_mapping() and a del_mapping() was created instead, to be usedby
both by remove_map() and globalize_table().
A test covering this case should definitely be created but that'll come
later. Proper operation was verified through manual debug log
inspection for now.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
`isr.S` depends on `CONFIG_GEN_SW_ISR_TABLE`.
Do not build it if SW ISR table is not present.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Now that the unwind starts from mepc already, the symbol
name at the mepc reg is kinda redundant, so just remove it.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Created the `arch_stack_walk()` function out from the original
`z_riscv_unwind_stack()`, it's been updated to support
unwinding any thread.
Updated the stack_unwind test case accordingly.
Increased the delay in `test_fatal_on_smp`, to wait
for the the fatal thread to be terminated, as stacktrace can
take a bit more time.
Doubled the kernel/smp testcase timeout from 60 (default) to
120s, as some of the tests can take a little bit more than 60s
to finish.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
An architecture can indicate that it has an implementation for
the `arch_stack_walk()` function by selecting
`ARCH_HAS_STACKWALK`.
Set the default value of `EXCEPTION_STACK_TRACE_MAX_FRAMES` to
`ARCH_STACKWALK_MAX_FRAMES` if the latter is available.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This code was never formally tested before... and without the preceding
commit it obviously didn't work either.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Existing code confused table usage and table reference counts together.
This obviously doesn't work. A table with one reference to it and one
populated PTE is not the same as a table with 2 references to it and
no PTe in use.
So split the two concepts and adjust the code accordingly. A page needs
to have its PTE usage count drop to zero before the last reference is
released. When both counts are 0 then the page is free.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This is part of a series of move memory management related
stuff out of Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Also any demand paging and page frame related bits are
renamed.
This is part of a series to move memory management related
stuff out of the Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is part of a series to move memory management related
stuff from Z_ namespace into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is part of a series to move memory management functions
away from the z_ namespace and into its own namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is part of a series to move memory management functions
away from the z_ namespace and into its own namespace. Also
make documentation available via doxygen.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is part of a series to move memory management functions
away from the z_ namespace and into its own namespace. Also
make documentation available via doxygen.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This renames z_phys_map() and z_phys_unmap() to
k_mem_map_phys_bare() and k_mem_unmap_phys_bare()
respectively. This is part of the series to move memory
management functions away from the z_ namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
isr_wrapper has been converted to C but this inline comment was not
updated. This fixes the out-of-sync comment.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Move this to a call in the init process. arch_* calls are no services
and should be called consistently during initialization.
Place it between PRE_KERNEL_1 and PRE_KERNEL_2 as some drivers
initialized in PRE_KERNEL_2 might depend on SMP being setup.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a prompt to ROMSTART_RELOCATION_ROM configs to allow
projects config file selection.
This simplifies the usage in samples/app for board porting.
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
Removed an unnecessary cast to void * from a function that already
had the correct signature.
This makes for more portable code as casting between code and data
pointers are frowned upon by the C standard.
Signed-off-by: Lars-Ove Karlsson <lars-ove.karlsson@iar.com>
Memory region defined in devicetree can have attributes
that are not intended to be parsed by MPU library,
but might be valid for other components.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Platforms that support IPIs allow them to be broadcast via the
new arch_sched_broadcast_ipi() routine (replacing arch_sched_ipi()).
Those that also allow IPIs to be directed to specific CPUs may
use arch_sched_directed_ipi() to do so.
As the kernel has the capability to track which CPUs may need an IPI
(see CONFIG_IPI_OPTIMIZE), this commit updates the signalling of
tracked IPIs to use the directed version if supported; otherwise
they continue to use the broadcast version.
Platforms that allow directed IPIs may see a significant reduction
in the number of IPI related ISRs when CONFIG_IPI_OPTIMIZE is
enabled and the number of CPUs increases. These platforms can be
identified by the Kconfig option CONFIG_ARCH_HAS_DIRECTED_IPIS.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
With power managment is enabled, depending on the SoC power state
used when idle, the MMU may lose context and may need to be re-initialized.
When re-initializing the MMU, we must not re-create the page table
because it may overwrite changes done during the execution, but we still
need to set the asid and page table for the current context.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Created `GEN_OFFSET_STRUCT` & `GEN_NAMED_OFFSET_STRUCT` that
works for `struct`, and remove the use of `z_arch_esf_t`
completely.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Make `struct arch_esf` compulsory for all architectures by
declaring it in the `arch_interface.h` header.
After this commit, the named struct `z_arch_esf_t` is only used
internally to generate offsets, and is slated to be removed
from the `arch_interface.h` header in the future.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The CLIC requires that mtvec.base is aligned to 64 bytes.
_isr_wrapper is used as mtvec.base, so align it to 64 bytes.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
The irq_offload mechanism was using the same entry of the IDT vector for
all CPUs on SMP systems. This caused race conditions when two CPUs were
doing irq_offload() calls.
This patch addresses that by adding one indirection layer: the
irq_offload() now sets a per CPU entry with the routine and parameter to
be run. Then a software interrupt is generated, and a default handler
will do the appropriate dispatching.
Finally, test "kernel/smp_abort" is enabled for x86 as it should work
now.
Fixes#72172.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Fix the dependencies of `CONFIG_EXCEPTION_STACK_TRACE`:
- Architecture-specific Kconfig, i.e.
`X86_EXCEPTION_STACK_TRACE`, will be enabled automatically
when all the dependencies are met.
- `EXCEPTION_STACK_TRACE` depends on architecture-specific
Kconfig to be enabled.
- The stack trace implementations should be compiled only if
user enables `CONFIG_EXCEPTION_STACK_TRACE`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Currently, the stack trace in ARM64 implementation depends on
frame pointer Kconfigs combo to be enabled. Create a dedicated
Kconfig for that instead, so that it is consistent with x86 and
riscv, and update the source accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The `DEBUG_INFO` in the `EXCEPTION_STACK_TRACE` is only
required by x86. Move that to `X86_EXCEPTION_STACK_TRACE`
instead.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
In some cases, the `fp` will never be `NULL` and the stack
unwinding can go on and on forever, limit the max depth so that
this will not happen.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
For SoC with `CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET`,
it should be taken into consideration when disconnecting IRQ.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Change the type of `cpu_id` to `uint8_t` since that is the type
of `arch_curr_cpu()->id`.
Instead of using precompiler switch (`#ifdef CONFIG_SMP`), use
if-else shorthand instead (`IS_ENABLED(CONFIG_SMP)`).
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.
Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.
Updated the includes path of in-tree sources accordingly.
Most of the changes here are scripted, check the PR for more
info.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Make sure that esf is not NULL before calling
z_riscv_unwind_stack to prevent NULL pointer dereferencing.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Regarding recent changes in general MPU configuration
(https://github.com/zephyrproject-rtos/zephyr/pull/71969), add
appropriate configs for isolating thread stacks into ARC MPU.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Use the multi-level interrupt APIs that accepts `level` as an
argument for the code where the level of the interrupt is not
known at build time.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Previously the multi-level irq lookup table is generated by
looping through the devicetree nodes using macros & Kconfig,
which is hard to read and flimsy.
This PR shifts the heavy lifting to devicetree & DT macros such
that an interrupt controller driver, which has its info in the
devicetree, can register itself directly with the multi-level
interrupt architecture, which is more straightforward.
The previous auto-generated look up table with macros is now
moved in a file of its own. A new compatibility Kconfig:
`CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is added and
enabled by default to compile the legacy look up table for
interrupt controller drivers that aren't updated to support the
new architecture yet.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Current on x86 & risc-v that implement stack trace, the
maximum depth of the stack trace is defined by a macro.
Introduce a new Kconfig:EXCEPTION_STACK_TRACE_MAX_FRAMES
so that this is configurable in software.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Selecting `CONFIG_SYMTAB` will
enable the symtab generation which will be used in the
stack trace to print the function name of the return
address.
Added `arm64` to the `arch.common.stack_unwind.symtab` test.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The mepc register is the address of the instruction that was
interrupted, it will make debugging easier if we know the
name of the symbol, so print it if `CONFIG_SYMTAB` is enabled.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Selecting `CONFIG_EXCEPTION_STACK_TRACE_SYMTAB` will
enable the symtab generation which will be used in the
stack trace to print the function name of the return
address.
Updated the `stack_unwind` test to test the symbols in a
stack trace.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Existing solutions for linking the Xtensa vector table are a
cut-and-paste mess of inherited code, with more than a dozen special
sections that need to be linked into many special MEMORY{} regions.
Accept the existing convention used by C/asm code, but automatically
detect the needed offsets for the platform from core-isa.h (it can
share the preprocessing with gen_zsr.py) and emit a file that can be
included in lieu of all the existing boilerplate.
Signed-off-by: Andy Ross <andyross@google.com>
RISC-V PMP implementation supports isolating thread stacks
within the same memory domain, and also is the only
supported operating mode. So select the corresponding
kconfig by default.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
ARM MPU implementation supports isolating thread stacks
within the same memory domain, and also is the only
supported operating mode. So select the corresponding
kconfig by default.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Declutter `fatal.c` by moving the stack unwinding logic into
`stacktrace.c` and guard its compilation with `CMakeLists.txt`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The original code would (unsurprisingly) only emit handler functions
for interrupt levels with interrupts associated with them. But it
turns out that it's possible to configure an xtensa device with an
empty-but-otherwise-real interrupt level (specifically mt8195 has a
"Level 3" interrupt not associated with any input IRQS, it's one level
above EXCM_LEVEL and one level below the DEBUG exception).
This script is old, and not set up to parse the full core-isa.h
directly, so modifying it to detect this condition is difficult.
Instead, just emit all 15 possible interrupt handlers, even empty
ones. The extra stubs are harmless as they'll be dropped if uncalled.
Signed-off-by: Andy Ross <andyross@google.com>
Some oddballs cores can be generated without an "NMI" interrupt, in
which case core-isa.h will not define XCHAL_NMILEVEL. This code is
trying to unconditionally mask interrupts, so XCHAL_EXCM_LEVEL is the
pedantically correct choice anyway (NMI's by definition, cannot be
masked).
Signed-off-by: Andy Ross <andyross@google.com>
The script to generate the _soc_inthandlers.h header has been run
manually for years, only because I was a cmake novice at the time and
unsure how to integrate it into the build. So every new platform has
to find the script and template file and figure out how to generate
the file. And in a few cases it looks like we've tried to EDIT the
resulting files in the tree.
Let's finally do this right. The file is now dropped (for every
xtensa platform) as a "xtensa_handlers.h" file, and there is a Kconfig
to control whether the original/manual file or the new one is used by
the platform code. We can migrate the other platforms slowly as
people have time to validate.
Signed-off-by: Andy Ross <andyross@google.com>
s2ram procedure used RAM magic word for marking suspend-to-RAM. This
method may not work in some cases, e.g. when global reset does not
reset RAM content. In that case resuming from s2ram is detected when
global reset occurred.
RAM magic word method is the default but with
CONFIG_PM_S2RAM_CUSTOM_MARKING a custom implementation can be provided.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
In order to support Linux rproc loading, some SOCs require
the boot-vector and irq-vectors to be placed into a defined
memory area for the mcu to boot.
This is necessary for NXP's IMX SOCs for instance but
can be leveraged by other SOCs that have multiple
zephyr,flash choices.
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
The only page table duplicated is the kernel page table. This function
does not need a parameter.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We can use some extra bits available for SW implementation to
save original permissions and avoid duplicating the kernel page tables
for the default memory domain.
Whe duplicating the page table to a new domain we just ensure
to restore the original map.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Simplify the logic around the shared attribute. Checks if a memory
region should be shared only in the function that actually maps the
memory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Remove the limitation of number of cpu support in x86 arch.
Also add support for retrieve cpu informations such as for
hybird cores.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Introduce z_page_frame_set() and z_page_frame_clear() to manipulate
flags. Obtain the virtual address using the existing
z_page_frame_to_virt(). This will make changes to the page frame
structure easier.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Change the GCC toolchain configuration to make use of the Cortex-R82
target. When Cortex-R82 was added as a GCC toolchain option, the GCC
version of the Zephyr SDK did not support Cortex-R82 tuning. Zephyr was
therefore compiled compiled for the Armv8.4-A architecture. Since Zephyr
SDK 0.15.0 (which updated GCC from 10.3.0 to 12.1.0) coupled with Zephyr
3.2, the Cortex-R82 target is supported.
The Armv8-R AArch64 architecture does not support the EL3 exception level.
EL3 support is therefore made conditional on Armv8-R vs Armv8-A.
Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>
Use `z_riscv_fatal_error_csf` that expects the
callee-saved-registers pointer only if `CONFIG_EXCEPTION_DEBUG`
is enabled, otherwise use `z_riscv_fatal_error`, as there can
be garbage in the `a2`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Change the character used to indicate immediate operands from '$' to '#'
to resolve an "invalid instruction" error when building with clang.
For arm, binutils allows either '#' or '$' to indicate immediate operands.
clang seems to accept '$' for arm in other instances
(my build accepts 'subs r0, r0, $0x02', for example), but in this case it
produces an error that this is an invalid instruction due to the "$0x02"
operand.
Given clang's inconsistent behavior, I'm guessing this is a bug in clang
somewhere, but:
1. '#' for immediate operands seems to be more standard for arm in
general and seems to be what is used throughout the rest of Zephyr's
arm asm code.
2. Switching out '$' for '#' shouldn't negatively impact other
toolchains.
As such, switch out the character used to unblock clang builds until this
can be fixed in clang.
Signed-off-by: Jonathon Penix <jpenix@quicinc.com>
LOG which IRQn line is triggering on spurious IRQs as this makes it
much easier to debug spurious IRQs.
The new logs with this patch looks like:
<err> os: Unhandled IRQn: 227
<err> os: >>> ZEPHYR FATAL ERROR 1: Unhandled interrupt on CPU 0
<err> os: Current thread: 0x20032c20 (unknown)
<err> os: Halting system
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Move the kconfig options used to configure the interrupt
and wait time to the sample which uses them instead of
having them in the architecture code.
This options are very particular for this sample and not
really an API.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This option can be used now also with native_sim
and seems to work fine with both 32 and 64 bit targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Move the LLVM fuzzing specific code out of the board main
file and into the sample.
That way we avoid needing to duplicate it for native_sim and
avoid having a very adhoc interface between the fuzzer test
and runner code.
Also ensure it works for native_sim and not just native_posix
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Compilers predefine system-specific macros which carry information about
compiler, target architecture and operating system. It provides basic
compiler-dependent information like size of types, their maximal and
minimal values, etc. It allows to write common libc headers for multiple
architectures and operating systems.
These macros allow code to always determine what is the target operating
system. This is a problem when compiling code of modules that supports
multiple operating systems (e.g. cryptography libraries).
To avoid confusion we shouldn't leak host operating system macros (e.g.
__linux__, __linux, linux, etc.) when compiling for native_sim board.
Unfortunately, there is no single universal switch that disables all
operating system macros:
- '-undef' removes also architecture-related macros
- '--target' is only available for Clang compiler
This patch uses '-include' option to include file that undefines all
well-known operating system macros.
Run 'gcc -dM -E - < /dev/null | sort' to get full list of predefined
macros.
Signed-off-by: Patryk Duda <patrykd@google.com>
Found via static analysis. In fault path when checking for stack
overflows, if CONFIG_MULTITHREADING is not set, `guard_end` is left
uninitialized and is subsequently used in a comparison.
The solution is to simply return `false` in this configuration as stack
guards are not configured in the first place.
Signed-off-by: François Baldassari <francois@memfault.com>
When duplicating a page table, we don't need to copy
the mapping to the kernel l1 page table virtual address.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
`CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET` shoud be taken into
account in `arch_irq_connect_dynamic`, same as it is done in
`ARCH_IRQ_CONNECT` macro.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
This also fixes a typo in `z_arm_switch_to_main_no_multithreading` making
it unlock irq instead of locking them when main returns.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Replace the global CSTD property with the CSTD kconfig option to select
at least C11 standard.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Influenced heavily by the RISCV64 stack unwinding
implementation in the Linux kernel.
`CONFIG_RISCV_EXCEPTION_STACK_TRACE` can be enabled by
configuring the following Kconfigs:
```prj.conf
CONFIG_DEBUG_INFO=y
CONFIG_EXCEPTION_STACK_TRACE=y
CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT=y
CONFIG_OMIT_FRAME_POINTER=n
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This mistake was introduced when converting from ASM to C.
This change also restores the associated comment from the ASM source.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This is a fix for #61761 where a cooperative task is switched from at the
end of an exception. A cooperative thread should only be switched from if
the thread exists the ready state.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This change significantly enhances the maintainability & portability of the
code at the expanse of an indirection (1 outlined function).
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This change reduces the need for core specific conditional compilation and
unifies irq locking code.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
# Conflicts:
# soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This change reduces the need for core specific conditional compilation.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.
This is a first step in reducing the amount of ASM in arch/arm/cortex_m
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
v* register aliases are uncommon and it can be surprising to find them.
This change makes use of r* register names for a more consistent
experience of reading assembly.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This method has special ABI requirement that requires the use of ASM.
This change documents why this is required & adds reference to the
related specification.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
A workaround to avoid icache corruption was added in commit be881d4cf2
("arch: xtensa: add isync to interrupt vector").
This patch implements a different workaround by adding custom logic to
idle entry on affected Intel ADSP platforms. To safely enter "waiti"
when clock gating is enabled, we need to ensure icache is both unlocked
and invalidated upon entry.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Only request the linker to link ASAN in the final stage, not
during the partial linking stage.
This fixes a link issue when building with llvm.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
If the CONFIG_ASAN_RECOVER option is set, also pass
-fsanitize-recover=all to the build of the native simulator
built files.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Currently LLEXT on Xtensa supports relocatable extensions, linked for
a specific address range, while relocation itself takes place in a
temporary buffer. For this section addresses have to be set correctly
by the linker for their target locations.
This commit adds support for relocatable extensions, built without
using specific memory addresses and run at the same addresses, where
they are loaded.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Adds support for all relocation type produced by GCC
on ARM platform using partial linking (-r flag) or
shared link (-fpic and -shared flag).
Signed-off-by: Cedric Lescop <cedric.lescop@se.com>
This adds the necessary bits to enable memory mapping thread
stacks on both x86 and x86_64. Note that currently these do
not support multi level mappings (e.g. demand paging and
running in virtual address space: qemu_x86/atom/virt board)
as the mapped stacks require actual physical addresses.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This introduces support for memory mapped thread stacks,
where each thread stack is mapped into virtual memory
address space with two guard pages to catch
under-/over-flowing the stack. This is just on the kernel
side. Additional architecture code is required to fully
support this feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Previous commit changed the privileged stack size to be using
kconfig CONFIG_PRIVILEGED_STACK_SIZE instead of simply
CONFIG_MMU_PAGE_SIZE. However, the stack bound check function
was still using the MMU page size, so fix that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Most places use CONFIG_X86_STACK_PROTECTION, but there are some
places using CONFIG_HW_STACK_PROTECTION. So synchronize all
to use CONFIG_X86_STACK_PROTECTION instead.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some toolchains cannot create shared objects for Xtensa, with them we
have to use relocatable objects. Add support for them to llext.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit removes the `Kconfig.core` file. It's been largely unused, and
the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer
provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`.
As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
When thread stack is defined as an array, K_THREAD_STACK_LEN()
is used to calculate the size for each stack in the array.
However, standalone thread stack has its size calculated by
Z_THREAD_STACK_SIZE_ADJUST() instead. Depending on the arch
alignment requirement, they may not be the same... which
could cause some confusions. So align them both to use
K_THREAD_STACK_LEN().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When kernel stack is defined as an array, K_KERNEL_STACK_LEN()
is used to calculate the size for each stack in the array.
However, standalone kernel stack has its size calculated by
Z_KERNEL_STACK_SIZE_ADJUST() instead. Depending on the arch
alignment requirement, they may not be the same... which
could cause some confusions. So align them both to use
K_KERNEL_STACK_LEN().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simple rename to align the kernel naming scheme. This is being
used throughout the tree, especially in the architecture code.
As this is not a private API internal to kernel, prefix it
appropriately with K_.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simple rename to align the kernel naming scheme. This is being
used throughout the tree, especially in the architecture code.
As this is not a private API internal to kernel, prefix it
appropriately with K_.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This call is used by syscalls machinery, and needs to be available for
extensions that use syscalls on ARM.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
arch_interface.h is for architecture and should not be
under sys/. So move it under include/zephyr/arch/.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There was old code to exit the simulator when there is a fatal
error. This updates the #ifdef and the function name so that
it can be used to exit both QEMU and simulator when a fatal
error occurs. This should help with twister runs as this will
fail immediately instead of having wait for timeout.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The #pragma to ignore array bounds for xtensa_soc_mmu_ranges[]
was a remnant before code refactoring during review. Since
this array is no longer declared __weak and as a zero length
array, the #pragma to ignore array bounds is no longer needed.
So remove them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
During early boot in assembly, the function parameter to
z_x86_early_tls_update_gdt() should be the pointer to
the interrupt stack. However, what was passed instead
was the pointer to the x86_cpuboot struct. So fix it to
actually pass the stack pointer (which is stashed inside
the x86_cpuboot struct).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
- spill windows in the current context (before switching task) since
it will be erased.
- Remove unnucessary load/mov
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
According to RISC-V Instruction Set Manual Chapter 3.3.2:
"The operation of WFI must be unaffected by the global interrupt
bits in mstatus
[...]
WFI is also required to resume execution for locally enabled
interrupts pending at any privilege level,
regardless of the global interrupt enable at each privilege level."
Disabling interrupts before executing `wfi` prevents a corner case
where an IRQ is presented just before executing `wfi`,
which would cause it to return directly into `wfi` and potentially
get stuck in sleep, instead of continuing to background processing.
When execution is resumed, interrupts are reenabled
and appropriate IRQ Handlers should be executed.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Some old references to native_posix are better
refering to the native targets in general,
or being clarified as only applying to the old
native_posix like targets.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This allows the SoC to have total control on what MPU ranges
to be programmed at boot. This overrides the generic ranges
in the architecture core code.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Both CONFIG_XTENSA_SYSCALL_USE_HELPER and
CONFIG_XTENSA_INSECURE_USERSPACE are also applicable to MPU.
So move them out of the CPU_HAS_MMU block.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For CPU without THREADPTR, we need an alternative way to figure
out if we are in user context. This extends the user context
check to do that via a brief syscall.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Calling z_mrsh_* functions require 7 arguments where the 7th is
the stack frame. Only the first 6 arguments are passed by
registers where the 7th must be done via stack. However, this
is not being done and an incorrect argument was being passed to
the z_mrsh_* functions as stack frame pointer. An obvious issue
would be dumping of stack during kernel oops, as incorrect data
was being printed or crashes due to inaccessible memory. So fix
it by properly populating the stack with correct stack frame
pointer as outgoing argument for the caller of z_mrsh_*
functions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need to do a call4 and jx. Simply do a callx4
is enough.
Also amended the now incorrect comment about how syscall
trampoline is set up. It is now a straight call4 instead of
the old 2x call4.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
POSIX has a custom implementation for thread abort
(z_impl_k_thread_abort) which lacks the tracing function
calls as in the generic version. So add them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
ARM/Cortex-M has a custom implementation for thread abort
(z_impl_k_thread_abort) which lacks the tracing function
calls as in the generic version. So add them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
On Intel ADSP platforms, additional "isync" is needed in interrupt
vector to synchronize icache when core is woken up from deeper
sleep state by an interrupt. This is only needed if DSP clock
gating is enabled.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Let's fix the error messages:
* native_posix is in general replaced with native_sim
* let's use hwmv2 names
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Replace uses of native_[posix,sim]_64 in the documentation
and kconfig help messages with native_[posix,sim]/native/64
to match the hwmv2 naming.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add support for the relocation type R_ARM_ARM_THM_CALL which is
produced for the ARM Thumb BL and BLX (branch immediate)
instructions.
These instructions are used for non-static functions like
void test1(void)
{
}
void main(void)
{
test1();
}
Without support for this relocation, test1() has to be static.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
The opval argument of arch_elf_relocate() was modified by
adding the value stored at opaddr before passing it to
arch_elf_relocate(). This presumed that the addend would
always be stored as a raw value at opaddr, which is not the
case for all relocation types.
This PR modifies opval to be the absolute address of opval,
and moves the addition of the addend from llext_link_plt()
to the implementation of arch_elf_relocate().
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
RASID must not use 0 for any slot. According with documentation:
"""The operation of the processor is undefined if any two of the
four ASIDs are equal or if it contains an ASID of zero"""
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Configure a new Kconfig (`CONFIG_RISCV_HART_MASK`) so that it
is possible to mask the `mhartid` of a processor. This is
helpful in the cases when the hart id starts from non-zero
value.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
There is a #endif comment which was incorrectly marked with
CONFIG_HW_STACK_PROTECTION instead of
CONFIG_ARM64_STACK_PROTECTION, which is used at #if.
So update it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Instead of using CONFIG_MMU_PAGE_SIZE for size of the privileged
stack, use the actual kconfig CONFIG_PRIVILEGED_STACK_SIZE.
This allows for changing the size of privileged stack, and
also aligns to the usage of CONFIG_PRIVILEGED_STACK_SIZE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Instead of using CONFIG_MMU_PAGE_SIZE for size of the privileged
stack, use the actual kconfig CONFIG_PRIVILEGED_STACK_SIZE.
This allows for changing the size of privileged stack, and
also aligns to the usage of CONFIG_PRIVILEGED_STACK_SIZE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are two kconfigs that are security related and are x86
specific. Prefix them with X86 to put them under the x86
namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds the necessary code required to unconditionally save/restore the
HiFi AE registers. The macros xchal_cp1_load and xchal_cp1_store
are defined in the Xtensa HAL.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Updates the xtensa_irq_base_save_area structure to include space
for saving/restoring the HiFi AudioEngine registers used by CP1.
The starting address of these HiFi AE registers also needs to be
referenced from assembly, so it is added to the set of symbols
symbols for which we need an offset to be auto-generated.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
This was part of the mega hwmv2 commit. Looks like hpet drivers heavily
relies on soc.h. Reverting this for now while we look for a proper fix
and remove reliance on soc.h for drivers.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some Xtensa cores do not support NMI, so XCHAL_HAVE_NMI=0 and
XCHAL_NMILEVEL won't be defined at all causing
arch/xtensa/include/xtensa-asm2-s.h to throw compilation error.
Fixes: #67855
Signed-off-by: Maciej Kusio <maciejkusio@meta.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Because the riscv32/riscv64 is redundant, one can get the same
information combining CONFIG_ARCH + CONFIG_64BIT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Fixes z_isr_install() and z_isr_uninstall() routines to check the isr
table index against the correct number of isr table entries. This
prevents out-of-bounds isr table accesses when
CONFIG_GEN_IRQ_START_VECTOR is greater than zero, such as on the ARC
architecture.
Coverity-CID: 347187
Coverity-CID: 347189
Coverity-CID: 347097
Coverity-CID: 347203
Coverity-CID: 347210
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Use _current_cpu->id instead of CURR_CPU since that works
with/without multicore and contains additional checks.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Some applications turn logging off. It makes impossible to get information
about exceptions if it occures.
This PR restores correct behavior of Error_Dump messages, and
exception dump is printed anyway independent on CONFIG_LOG.
ARC_EXCEPTION_DEBUG added to default boards configs in addition to nsim.
CONFIG_FAULT_DUMP removed from ARC branch as it has been unused
since v1.8.0
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
This fix removes the zephyr/ prefix from linker included files.
With this prefix the build works only for Ninja and not for
other build tools.
Linking in Zephyr / CMake:
- Ninja invokes linking directly from <build>.
- Make invokes linking form <build>/zephyr.
The linker default uses cwd for looking up INCLUDE directives if not found
in list of includes.
Zephyr always adds <build>/zephyr as link include using CMake,
and this is passed to ld as -L<build>/zephyr therefore using
INCLUDE isr_tables_swi.ld ensures it will be correctly found in all cases.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit removes the need of swi_tables.ld file if the
ISR table generator is not configured to use it.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit updates the arm and arm64 architecture files
to support the new ISR handlers creation parser.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit implements the possibility to locally create an interrupt
table entry. This changes the way interrput table is created,
now it should not be created as an source file but rather it would be
constructed by the linker.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit moves all the functionality related to the current
interrupt parser into gen_isr_tables_parser_carrays.py file.
The new parser file gen_isr_tables_parser_local.py file is
implemented with the new parser that.
Additional information added to the generated interrupt header
that contains data required by the new parser.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit updates the definition of z_shared_isr_table_entry
to use _isr_table_entry instead of specially created z_shared_isr_client.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
This commit adds missing __used attribute it int_list_header,
preventing it from being optimized out.
Signed-off-by: Radosław Koppel <radoslaw.koppel@nordicsemi.no>
The ZSR_FLUSH scratch register is only needed if kconfig
CONFIG_KERNEL_COHERENCE is enabled. So update gen_zsr.py
for that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Print THREADPTR when dumping stack just like other registers.
There is no need to guard that behind CONFIG_USERSPACE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
add interface for encode irq flags from acpica to arch specfic.
Currently enabled only for x86 archiecture.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Disable Thread Local Storage for some configurations of ARC architecture.
For cores with more then one RGF_NUM_BANKS the parameter is disabled
by-default because banks syncronization requires significant time,
and it slows down performance.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
In case of ARCv3 we have shared cache disabled after
reset (in ARCv2 it was enabled by default). Let's
enable it at early boot phase (if it's available in HW).
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
ARCv3 processors have HW prefetch feature which is disabled
after reset. Let's enable it.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
When COMPILER_WARNINGS_AS_ERRORS is set, let's also have the
native simulator runner (and anything Zephyr requests built with it)
be built with the same option to treat warnings as errors.
Otherwise we will miss those by default in CI.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The arm64_cpu_boot_params will be read on other cores
call sys_cache_data_flush_range flush the data from the cache to RAM.
This ensures that other cores can access the correct data.
Signed-off-by: honglin leng <a909204013@gmail.com>
Do not define these macros globally, but instead
define them only for this library and when needed.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This constant is supposed to be defined as a long instead of an int,
presumably to support systems where int isn't large enough.
Signed-off-by: Keith Packard <keithp@keithp.com>
Disabling the MPU doesn't clear regions configuration. There is a risk
in multi-image environment that there are some old region setting e.g.
stack guard. This may cause a memory fault, because of different images
layout e.g. RO/RW.
Just clear and disable all regions configuration before the new
initialization.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
It looks like some soc_offsets.h files need to be included before
kernel_offsets, otherwise there are some header race conditions due to
the infamous soc.h. This problem is exposed if all soc.h are removed
from RISC-V arch header files (see the upcoming commits). It can be
reproduced by building rv32m1_vega_ri5cy board after applying all the
patches in this series (excluding this one, of course).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
There is no need to sync in every xtlb invalidation. Sync only
after all tlb autofill ways invalidation.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Xtensa's arch level atomic implementation requries S32C1I
support which may not exist as Xtensa cores are highly
configurable. Implying CONFIG_ATOMIC_OPERATIONS_ARCH at
arch level has a side effect that it is enabled
regardless if the other options are enabled. Given how
the header file's #ifdef is structured, only C atomic
ops can override this, which means enabling
CONFIG_ATOMIC_OPERATIONS_BUILTIN has no effect at all.
So let the SoC or board decide which atomic ops are
being used instead.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
According to the clic specification
(https://github.com/riscv/riscv-fast-interrupt), the mnxti register has
be written, in order to clear the pending bit for non-vectored
interrupts. For vectored interrupts, this is automatically done.
From the spec:
"If the pending interrupt is edge-triggered, hardware will automatically
clear the corresponding pending bit when the CSR instruction that
accesses xnxti includes a write."
I added a kconfig `RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING` to allow custom
irq handling. If enabled, `__soc_handle_all_irqs` has to be implemented.
For clic, non-vectored mode, I added a `__soc_handle_all_irqs`, that
handles the pending interrupts according to the pseudo code in the spec.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
The irq priority has to be called for dynamic and direct irqs, too. For
direct isrs, this was missing completely, for direct irqs just for the
clic.
For dynamic irqs, I replaced the current implementation with
`z_riscv_irq_priority_set`. For the plic, this is exaclty the same.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
For some reason, unrelated code change triggered compiler
warning about this function returns even though it is
marked nonreturn. So add CODE_UNREACHABLE to silence
the warning, possibly to catch any errors.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
wsr.UPPERCASE can lead to compiler errors when UPPERCASE matches
a macro defined in the special register header file.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
rsr.UPPERCASE can lead to compiler errors when UPPERCASE matches
a macro defined in the special register header file.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Instead of custom SOC_MCAUSE_EXP_MASK definition. Note that SoCs
selecting RISCV_PRIVILEGED already used such config indirectly (see
changes in soc_common.h).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As defined in Table 3.6 of "The RISC-V Instruction Set Manual, Volume
II: Privileged Architecture". Delete all spread definitions of the same,
weirdly prefixed with "SOC".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Initial implementation of `sched_getparam()` and `sched_getscheduler()`
POSIX APIs as a part of PSE53 `_POSIX_PRIORITY_SCHEDULING` option group.
Both functions are actually placeholders and just return `ENOSYS`
since Zephyr does not yet support processes or process scheduling.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Because it was exclusively used by the "common" RISC-V privileged code
to build CPU idle routines that are now handled by arch level code.
Also, all platforms defaulted to "y", making it pointless in practice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
While going to idle may require SoC specific implementations, provide a
more sensible default implementation.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The constant used to calculate TLB entries for the way six was wrong
and causing an integer overflow. Consequently only the first 512MB where
being unmapped from the TLB.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Use the arch-cache functions instead of the sys-cache-functions
in z_arm_init_arch_hw_at_boot to ensure that the caches are
disabled even when CONFIG_CACHE_MANAGEMENT is disabled.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use sys_cache_data_enable instead of arch_dcache_enable to enable
the cache. This will ensure that CONFIG_CACHE_MANAGEMENT
is considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The interface to flush fpu is not unique to one architecture, make it a
generic, optional interface that can be implemented (and overriden) by a
platform.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Different architecture are doing this in custom ways and using different
naming conventions, unify this interface and make it part of the arch
implementation for SMP.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.
Note that the SoC family naming scheme will be fixed in upcoming
commits.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This adds a kconfig to enable invalidating the TLBs related to
the incoming thread's memory domain during page table swaps.
It provides a workaround, if needed, to clear out stale TLB
entries used by the thread being swapped out. Those stale
entries may contain incorrect permissions and rings.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are several subsystems and boards which require a relatively large
system heap (used by k_malloc()) to function properly. This became even
more notable with the recent introduction of the ACPICA library, which
causes ACPI-using boards to require a system heap of up to several
megabytes in size.
Until now, subsystems and boards have tried to solve this by having
Kconfig overlays which modify the default value of HEAP_MEM_POOL_SIZE.
This works ok, except when applications start explicitly setting values
in their prj.conf files:
$ git grep CONFIG_HEAP_MEM_POOL_SIZE= tests samples|wc -l
157
The vast majority of values set by current sample or test applications
is much too small for subsystems like ACPI, which results in the
application not being able to run on such boards.
To solve this situation, we introduce support for subsystems to specify
their own custom system heap size requirement. Subsystems do
this by defining Kconfig options with the prefix HEAP_MEM_POOL_ADD_SIZE_.
The final value of the system heap is the sum of the custom
minimum requirements, or the value existing HEAP_MEM_POOL_SIZE option,
whichever is greater.
We also introduce a new HEAP_MEM_POOL_IGNORE_MIN Kconfig option which
applications can use to force a lower value than what subsystems have
specficied, however this behavior is disabled by default.
Whenever the minimum is greater than the requested value a CMake warning
will be issued in the build output.
This patch ends up modifying several places outside of kernel code,
since the presence of the system heap is no longer detected using a
non-zero CONFIG_HEAP_MEM_POOL_SIZE value, rather it's now detected using
a new K_HEAP_MEM_POOL_SIZE value that's evaluated at build.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This commit adds implementation of GDB stub for 32-bit ARM. It has been
tested only on the Zynq-7000 SoC and I would like to get any feedback
from others.
The stub still has these issues:
- To implement single stepping, it uses instruction address mismatch
breakpoint, as recommended in ARMv7 reference. The breakpoint control
register is configured (the state control fields) for the "PL0,
Supervisor and System modes only" option. Otherwise the breakpoint
would also halt the processor in abort mode, in which the stub loop
runs. Zephyr kernel runs in the system mode. This works well until the
kernel enables interrupts, as interrupt handlers typically run in
Supervisor mode. Single stepping therefore sometimes "catches" a
handler instead of the next application instruction. I have not tried
User mode, because Cortex-A SoCs do not appear to have the
ARCH_HAS_USERSPACE flag.
Cc: Michal Sojka <michal.sojka@cvut.cz>
Signed-off-by: Marek Vedral <marek.vedral@gmail.com>
The only difference in the two enums are some entries related to
relocation sections. However, these entries are not used in the
code, so they can be safely removed, along with the mapping function.
Use LLEXT_MEM_* to avoid confusion with low-level "section" names.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Change exception code to use LOG_ERR and align with all other
architectures when CONFIG_EXCEPTION_DEBUG is enabled.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
It should be possible to disable exception debug, which is enabled by
default to reduce image size. Add missing guards now that the option is
cross architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename xtensa_asm2.c to have a more meaningful name to actually
reflect the content of the file. This file is mostly about
handling interrupts and exceptions (via the predefined vectors
in Xtensa core).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
