Add initial support for the RP2350's DMA peripheral, allow tests
under drivers/dma/loop_transfer to run on on the Raspberry Pi Pico 2,
and update the board's documentation.
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add initial support for the RP2350's PIO peripherals, extend the
existing example under samples/boards/raspberrypi/rpi_pico/uart_pio to
demonstrate this on the Raspberry Pi Pico 2, and update the board's
documentation.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
Add OpenOCD debugger support.
For now we will need Raspberry Pi'a forked version of OpenOCD from
https://github.com/raspberrypi/openocd .
The default adapter speed is set to match Raspberry Pi's documentation.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Add UF2 Family ID for Raspberry Pi 2350 and build
UF2 image by default for Pico 2 board
Signed-off-by: Ryan Grachek <grachek@gmail.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
The Raspberry Pi Pico 2 is Raspberry Pi's first board fitted with their
RP2350A SoC.
This adds a minimal board definition, sufficient to build and run
`samples/hello_world` and `samples/basic/blinky` on the board. Images
can be run on the target using OpenOCD. Raspberry Pi's `picotool` can
create a UF2 binary, which ensures that errata RP2350-E10 is avoided
e.g.
```
> picotool uf2 convert build\rpi_pico2\hello_world\zephyr\zephyr.elf \
build\rpi_pico2\hello_world\zephyr\zephyr.uf2 \
--family rp2350-arm-s --abs-block`
```
Raspberry Pi Pico 2 is a low-cost, high-performance microcontroller
board with flexible digital interfaces. Key features include:
- RP2350A microcontroller chip designed by Raspberry Pi in the United
Kingdom
- Dual Cortex-M33 or Hazard3 processors at up to 150MHz
- 520KB of SRAM, and 4MB of on-board flash memory
- USB 1.1 with device and host support
- Low-power sleep and dormant modes
- Drag-and-drop programming using mass storage over USB
- 26x multi-function GPIO pins including 3 that can be used for ADC
- 2x SPI, 2x I2C, 2x UART, 3x 12-bit 500ksps Analogue to Digital
Converter (ADC), 24x controllable PWM channels
- 2x Timer with 4 alarms, 1x AON Timer
- Temperature sensor
- 3x Programmable IO (PIO) blocks, 12 state machines total for custom
peripheral support
- Flexible, user-programmable high-speed IO
- Can emulate interfaces such as SD Card and VGA
The Raspberry Pi Pico 2 comes as a castellated module which allows
soldering direct to carrier boards.
Only enable timer 0 for now. Timer 1 won't work correctly until the
rpi_pico HAL has picked up the fix for `hardware_alarm_irq_handler`. See
https://github.com/raspberrypi/pico-sdk/pull/1949 .
Added some documentation for the board itself (mostly aiming to refer to
canonical sources of information rather duplicate). Add entries in the
release notes where applicable.
boards/raspberrypi/rpi_pico2/doc/img/rpi_pico2.webp is a cropped and
compressed version of https://www.raspberrypi.com/documentation/microcontrollers/images/pico-2.png
which is released under the CC-BY-SA-4.0 license. See https://github.com/raspberrypi/documentation/blob/develop/LICENSE.md
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
A significant amount of the pin muxing is duplicated between the RP2040,
the RP2350A, and RP2350B. Reflect this in the file structure, with a
`-common` suffix used to to indicate this.
Macros are defined in ascending order of the function index in the
relevant table in the datasheet. SoC/SoC-series specific macros are
defined in their respective tables. Functions that are not currently
used (e.g. the new HSTX) are intentionally not defined here as they do
not (currently) have any use in the Zephyr tree (i.e. there's no drivers
that make use of this functionality).
clang-format has been run over the existing definitions to reduce the
noise generated by CI. These are cosmetic changes; I've tried to retain
attribution to the relevant authors where applicable.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Completes the PLLi2S configuration for this board based on stm32f411
with a PLLI2S compatible = "st,stm32f411-plli2s-clock";
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Completes the PLLi2S configuration for those boards based on stm32f4
with a PLLI2S compatible = "st,stm32f411-plli2s-clock";
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Added support for the SPI interface which is availble on the shield
if the jumper configurations are changed.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
- Enables a MCUboot support for frdm-mcxa156.
- Enables MCUMgr OTA and MCUBoot recovery for frdm-mcxa156.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Convert qspi and hyperflash to variants instead of revisions by popular
demand.
And convert evkb into a revision instead of a different board.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Rename "nxp,kinetis-ftm-pwm" compatible to "nxp,ftm-pwm" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
With recent SDSC bundles, 54H fails the app core boot in case of a
unsupported GPIO in the UICR.
As Wi-Fi SR co-existence on nRF54H20DK is not yet supported, remove this
GPIO for 54H. This will be fixed properly once co-existence is
revisited.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Removed FLASH_BASE_ADDRESS configuration from various boards' Kconfig.
The only thing needed in order to do this was to update the relevant dtsi
files so that the flash0 node has its reg property configured properly.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
This board has a built-in debug adapter that provides a serial
connection to the host. This is mentioned in the board documentation.
The SoC pins P0.15 (RX) and P0.19 (TX) are connected to the debug
adapter pins TXD and RXD, respectively. This board should not configure
any other serial connection by default.
Update the board documentation accordingly.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Test "drivers.gpio.1pin.aw9523b" fails on stm32u083c_dk platform
because "arduino_i2c" definition does not exists in the device tree
of stm32u083c_dk board. Also updated the baord yaml
Signed-off-by: Arif Balik <arifbalik@outlook.com>
Added aliases to nucleo_l4r5zi/stm32f4_disco/stm32f411e_disco for
die_temp die_temp/vref/vbat nodes so that the die_temp_polling
and soc_voltage samples work for them.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
The documentation incorrectly referred to the Semtech shield as
semtech_sx1271mb1mas. It should be semtech_sx1276mb1mas.
Signed-off-by: Sreeraj Sudhakaran <sreerajsudhakaran@gmail.com>
Now that MbedTLS is capable of automatically enabling
CONFIG_ENTROPY_GENERATOR (when available), we can remove forced
enablements in boards|soc deconfig files.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Creation of the new zephyr\soc\nxp\common\nxp_nbu.c driver which manage
the interruption of the NBU. This modification is mandatory to support a
coex application which includes Bluetooth and 802.15.4 on the same
narrow band path.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
Secure domain firmware v9.0.0 and onward no longer supports the
non-essential domain reset procedure which was used in the custom
JLink reset scheme for
nrf54h20dk/nrf54h20/cpuapp, nrf54h20dk/nrf54h20/cpurad,
nrf9280pdk/nrf9280/cpuapp and nrf9280pdk/nrf9280/cpurad.
All resets done through the ADAC interface now do a global reset
instead, which as of now "kills" the JLink session.
Remove the custom reset behavior as it will not work anymore moving
forward. This means that "monitor reset" in GDB can no longer be used
to debug the application from the start of execution. Using current
tooling, it is possible to debug from the start of execution by first
resetting the cores into a halted state, starting cores other than the
one you are debugging and then attaching GDB. For example:
> nrfutil device reset --reset-kind RESET_VIA_SECDOM
> nrfutil device go --core Network
> west attach
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This commit enables support for DMA,
SPI, RNG, Crypto, USB and RTC.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
The ecpprog command is an utility written by Greg Davill for flashing
FPGAs such as ECP5 or CrossLink-NX series. Devkits typically have an
FTDI interface chip to access the external flash. FPGA image is
typically at flash offset 0x00000000 flash offset, and the Zephyr
image offset can be set via CONFIG_FLASH_LOAD_OFFSET.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Shield was enabling some Kconfig options for no reason. Shields do
not need to enable driver classes unconditionally, these are enabled
either by drivers or samples that require them.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In all STM32 dtsi and board dts, update the st,adc-sequencer and the
st,adc-clock-source properties so they are strings.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
fu dts: arm: st: use string instead of enum
- Add "channel-available-mask" property in ADC node
to detect which channels are available to use
- Add "add-average-count" property in ADC node to chose
number of count of the addition or average mode
- Change the source code of ADC to match with 2 new properties.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use STM32_CLOCK() clock select macro with bit-25
set.
This change shall set register RCC_CCIPR->FDCANSEL
to 0x01.
Previosuly there were bit-12 set, which was wrong.
For more information refer to RM0440 Rev. 8
page 323 of 2138.
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
In nRF53 SoC, the CPUAPP owns all the GPIOs by default.
Therefore, even if the GPIOs are exclusively used by CPUNET,
we must redefine them for CPUAPP and then set up GPIO
forwarding to CPUNET using SoC registers (this is done as
part of the MPSL CX initialization).
Previously, these GPIOs were mistakenly removed from CPUAPP
and defined only for CPUNET. This caused the GPIOs to be
available for CPUNET but still owned by CPUAPP, breaking
SR coexistence.
Signed-off-by: Murali Thokala <Murali.Thokala@nordicsemi.no>
Introduce Google Icetower Development Board.
Icetower is a board created by Google for fingerprint-related
functionality development.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Add Toradex Verdin iMX8M Mini board based on NXP MIMX8MM EVK using the
i.MX8MM SoC. This code is intented to be used with the Cortex-M4.
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
add the i3c2 pin setting
set i3c2 instance as ok status
add p3t1755dp_ard_i3c_interface/p3t1755dp_ard_i2c_interface node label
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
When running tests on sam0 platform was detected that pinctrl for ADC
were not defined for some boards. To force an error at build time
nodes should be explicity disabled. This explicity disable nodes on
devicetree that require some user configuration.
In addition, the adc feature were excluded in some boards and
samr21-xpro was correct updated.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This allows to build samples by twister which depend on 'arduino_gpio',
'arduino_i2c', 'arduino_serial' and 'arduino_spi'.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
bicr.json is a supporting file that, if present and
CONFIG_SOC_NRF54H20_GENERATE_BICR=y (default), will be used to generate
a BICR hex file. The schema for the file can be found at
soc/nordic/nrf54h20/bicr/bicrgen-schema.json.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adds the device trees, Kconfig, and documentation files.
The following features have been confirmed working on hardware:
* LED
* SPI LCD
* UART
* W25Q64 SPI FLASH
Signed-off-by: zack jiang <1125934312@qq.com>
* Add documentation about nRF9161 SoC variant
* Modify example apps to include both nRF9161 and nRF52840
* Switch from DFU to MCUmgr in example apps
Signed-off-by: Jan Kowalewski <jkowalewski@cthings.co>
The board hardware has no network interfaces, although the ECM/EEM class
implementation can provide Ethernet-like functionality and export it to
the host, this is no reason to default to a specific USB class
implementation.We do not make this kind of configuration for other
boards that have a USB device controller. Also, it may not be what a
user expects when using these boards with networking and a USB stack.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Remove all USB and CDC ACM configuration in favor of common
configuraiton.
Do not adapt board-specific configurations such as unknown PID/VID or
string descriptors. There is no justification for using them on specific
boards, and we do not have formal approval to use them in the project
tree. Also, we need more uniform configuration, since the main reason
for enabling CDC ACM here is to allow users to run examples like
hello_world right out of the box. Of course, anyone is free to customize
these settings in their fork or downstream project.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Many boards have similar code to configure the USB and CDC ACM UART that
they want to use as a logging or shell backend. Some of them have an
incorrect or incomplete configuration.
These boards do not have a built-in debug adapter, but a SoC with a USB
device controller and a bootloader with USB device support. Introduce
common CDC ACM UART configuration that these boards should use for
logging or shell backend to avoid duplicate or incorrect configuration.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Update sltb010a,slwrb4180a, xg24_dk2601b and xg27_dk2602a boards
descriptions in order to run dma test. Also update boards
documentations.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Fix ICCM/DCCM properties both in DTS and in MDB settings to match the
original hardware configuration.
Signed-off-by: Ilya Tagunov <Ilya.Tagunov@synopsys.com>
As these boards are completely simulated and do not represent any real
hardware configurations anymore, provide them with 1M of both ICCM and
DCCM to avoid any out-of-memory test failures.
Signed-off-by: Ilya Tagunov <Ilya.Tagunov@synopsys.com>
Fix ICCM/DCCM properties in DTS to match the intended configuration,
along with some other minor inconsistencies.
Signed-off-by: Ilya Tagunov <Ilya.Tagunov@synopsys.com>
imx8qm and imx8qxp have a couple of differences regarding
the peripheral address spaces and how the DT nodes are
configured, which is why using a generic DTSI (nxp_imx8.dtsi)
for the both of them is not right.
One of the differences between the two, which affects Zephyr
is the fact that irqstr's address space is different. Up until
now this has been dealt with at the board level (i.e:
imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not
board-specific, but rather soc-specific. Additionally, this
causes the following warning during compilation:
"unit address and first address in 'reg' (0x51080000) don't
match for /interrupt-controller@510a0000"
To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp.
Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include
the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This updates openocd.cfg file to support flashing multiple boards
attached to the host computer.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
This reverts commit f6235e03cf.
Reason for revert:
The modifications introduced in this commit caused a problem
with the WebUSB.
As a result, these modifications are not needed and are being
reverted to restore proper operation of the WebUSB sample.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
This change brings in certain default configurations that are needed
for selection of random number generator, and to set tcp
configuration CONFIG_NET_TCP_ISN_RFC6528=n for nRF7002dk board.
Signed-off-by: Vivekananda Uppunda <vivekananda.uppunda@nordicsemi.no>
Add shield definition for the Mikroe ETH 3 Click.
ETH 3 Click is a compact add-on board that contains
LAN9250 SPI Ethernet Controller
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add support for UDC on highspeed port on these boards:
- ek_ra8m1
- ek_ra8d1
- ek_ra6m5
- ek_ra6m3
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Improve Simics support for `boards/intel/ish/intel_ish_5_8_0`
for better integration with the simulator.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for board RZ/G3S-SMARC
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This commit enables I3C support for STM32 nucleo_h563zi boards.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Due to Apollo3's internal bootloader, zephyr build is not able
to create correct flash address on linker.cmd while using
mcuboot. The PR configures flash-controller start address
to solve this problem.
Test board: rakwireless/rak11720
Test project: samples/subsys/mgmt/mcumgr/smp_svr
Signed-off-by: Sercan Erat <sercanerat@gmail.com>
Configure the TE signal for the rw_rw612_bga board when using the
lcd_par_s035 shield. This signal should be handled on the rising edge in
the default configuration, since the display writes from the MCU are
faster than the panel reads data.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This board has the required clock crystal (X4) and jumper settings
present to enable the USB 2.0 HS support.
* Enable the HSE clock (16MHz)
* Flip the PLL1 configuration over to use the HSE clock, but still
outputting 160MHz to sysclk/apbclk.
* Add the USB HS device tree node.
* Update the board documentation.
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Configure the Raspberry Pi Pico W for WiFi.
Move Pico W configuration details to devicetree
Add pinctrl configurations for data/interrupt sharing
Make memory config selectable
Align devicetree with Linux ordering
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
- Add support CAN-FD for EK-RA6E2, EK-RA4E2
- Enable ioport for can-transceiver on EK-RA6E2, EK-RA4E2
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
ENTROPY_GENERATOR is now automatically enabled if the board
has "zephyr,entropy" chosen property set, so there is no need
to manually select it.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Add the required code for `west debug` to work the FLPR
core over JLink in the nRF54L 05, 10 and 15 devices.
Note that this requries an external J-Link probe, it will not work with
the on-board (OB) probe soldered on the DK.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add entropy support for these boards: ek_ra6m1, ek_ra6m2, ek_ra6m3
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
drivers/input/input_gpio_keys.c requires property "zephyr,code" must
be provides for gpio-keys, so add code property for imx93_evk A55
and M33 boards.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Correct "zephyr,sram" property under /chosen node to make board and samples
compatible with new SoC memory description.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
This option gets the default value "y" whenever HAS_BT_CTLR is enabled, and
since the EFR32 HCI driver now selects HAS_BT_CTLR the right thing happens
either way.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
During migration to HWMv2 separate specific defconfig file was removed
for GICv3 version of virtual xenvm boards. It worked fine before
commit 0be0d2175b ("cmake: modules: extensions: Revert using common
board files") significantly changed build behavior, but did not return
previously removed file. This led to build/runtime issues, when some of
the Kconfig options were not selected.
Return GICv3 specific defconfig to board directory to fix configuration
problems.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
This makes minichlink the default runner for the ch32v003evt.
This way, `west flash` "just works", as advertised in the README, rather
than having to manually set the runner to `minichlink` for it to work.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The PINCTRL option is selected now by the drivers which use it, so
it's possible to remove it from the board defconfig.
Signed-off-by: Ilya Tagunov <Ilya.Tagunov@synopsys.com>
Enable i2c and configure it to read accelerometer sensor on the board.
Test it using sample.sensor.accel_polling.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
xenvm Kconfig contained incorrect name for board parameter. It led to
build issues - heap size was set incorrectly. Since whole file is
already placed under right Kconfig condition ("if BOARD_XENVM"), remove
incorrect parameter at all.
This issue was introduced by commit 8dc3f85622 ("hwmv2: Introduce
Hardware model version 2 and convert devices") due to the typo.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Added basic support for west debug for nrf54h20
RISC-V cpus: nrf54h20_cpuppr and nrf54h20_cpuppr.
Note external jlink probe needs to be used.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
This boards was merged before rp2040.dtsi changed location.
Update the include in its dts file accordingly
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Change whitespace to match the coding style for CMake files for all
rp2040-based boards.
This is foundation work ahead of adding support for boards based on the
RP235XX SoCs.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
No in-tree board uses this driver's pinctrl functionality, and every
RP2040-based board was configuring this to be an empty node in the
device tree, so remove them.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Follow the wider directory convention of dts/<arch>/<vendor>/<family>.
This is foundation work ahead of introducing support for the RP2350.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Enable Ethernet controller node and mdio node for RA boards.
Add pinctl for mdio and Ethernet usage
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
mcxc444 also has pit and rtc counters, add the counters to
board documentation, and enable it explicitly in board dts.
Set rtc clock to 32 kHz oscillator.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
