This patch adds a timeout to the clock_control_on() implementation. The
reason for this timeout is to prevent system freezes when the PLL is
configured incorrectly, or, if BICR is wrong. The locking time of the
AUXPLL is <30us, however, when it starts it also starts other
dependencies which take much longer to become ready. The locking time
has been experimentally measured to be around 2ms, so a 10x bound has
been added.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new driver for the AUXPLL peripheral found in some new Nordic
SoCs, e.g. nRF54H20. AUXPLL is used to clock some peripherals like e.g.
CAN. Note that driver is implemented natively as Nordic HAL lacks
definitions for the AUXPLL IP, this may be changed once these become
available.
Note that usage of nrf_auxpll_config_set generates unnecessary extra
assembly code compared to the proposed API in
https://github.com/zephyrproject-rtos/hal_nordic/pull/185 which
guarantees static initialization and single write access, possible in
the Zephyr context. However, current solution has been enforced until
further discussion on raw access APIs takes place.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
