Fix a compilation error occurring when a prescaler was set for ADC on F1
and F3 family.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
BDCR and PWR_CR could be required for LSE or RTC for instance.
Enable it here as for now, no sophisticated PM handling is available
on F0 and F3 series.
Fixes#56449
Fixup for #56505
Signed-off-by: Kay P <kayo@illumium.org>
BDCR could be required for LSE or RTC for instance.
Enable it here as for now, no sophisticated PM handling is available
on F3 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The SOC specific implementations of the clock_stm32_ll_common driver
included the PLL specific functions only when PLL was selected as sysclock.
This commit changes the condition from "STM32_SYSCLK_SRC_PLL"
to "defined(STM32_PLL_ENABLED)".
As a result the pll could also be used as peripheral clock source
in case it is not the sysclock.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Similarly to what was done on U5 and H7 clock_control drivers, enable
device clock source selection.
This is done by:
-providing implementation for clock_control_configure().
-updating clock_control_get_rate() to support various possible clock
sources (SYSCLK, PLLCLK, LSE, LSI, HSI, HSE).
-providing enable_clock() to verify requested clock source exists and
is enabled.
-adding LSI and LSE device tree based initialization to
set_up_fixed_clock_sources().
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.
To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.
The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.
Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We should not set PLLSRC bits here. It is done by
LL_PLL_ConfigSystemClock_* functions which are called later.
Also, PREDIV1 setting should not be restricted to HSE only.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
On stm32f302/3 series, USB and CAN_1 share same IRQ lines.
To use USB and CAN_1 together, USB IRQ could be remap to other
line numbers, on which there is no conflict.
Remap the USB IRQ lines by default:
-Assign remap number in matching dtsi files
-Perform remap before usb driver init
Additionally, fix compilation issue in usb driver.
Fixes#22343
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
RCC device could be common to various STM32 series.
Until now, PLL handling code was set in series specific files,
even if it was driving the same device than another series.
Minimize code duplication by factorizing code between series
when possible.
With this change, some series get additional features by getting
access to code developed for other series.
Additionally, while renaming the files, remove the non informative
'x' to minimize file name length
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-10 10:53:11 -04:00
Renamed from drivers/clock_control/clock_stm32f0x.c (Browse further)
