Add support for LAN8670/1/2 Rev.C2 as per the latest configuration note
AN1699 released (Revision E (DS60001699F - June 2024)) for Rev.C1 is also
applicable for Rev.C2. Refer hardware revisions list in the latest AN1699
Revision E (DS60001699F - June 2024).
https://www.microchip.com/en-us/application-notes/an1699
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Add support for LAN8650/1 Rev.B1. As per the latest configuration note
AN1760 released (Revision F (DS60001760G - June 2024)) for Rev.B0 is also
applicable for Rev.B1. Refer hardware revisions list in the latest AN1760
Revision F (DS60001760G - June 2024).
https://www.microchip.com/en-us/application-notes/an1760
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
10BASE-T1S PHYs can operate in either CSMA/CD or PLCA mode. PLCA mode
needs some set of parameters like node id, node count, max burst count,
burst timer and TO (Transmit Oppertunity) timer to be configured. OPEN
Alliance TC14 specification defined a set of PLCA registers to configure
PLCA mode. The below APIs are implemented for PLCA mode.
genphy_set_plca_cfg() - to configure PLCA settings.
genphy_get_plca_cfg() - to get the configured PLCA settings.
genphy_get_plca_sts() - to get the PLCA status like active or inactive.
These APIs are implemented as generic library so that all 10BASE-T1S
PHYs can use these APIs to configure/access PLCA settings to avoid
duplication of code.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Simplifies GPIO reset logic in `phy_mc_ksz8081_reset()` by introducing
a dedicated function, `phy_ksz8081_reset_gpio`. If this function returns
`-ENODEV`, it will fall back to using a command-based reset instead.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Simplifies error handling in `phy_mc_ksz8081_get_link()` by
centralizing mutex unlocking with a `done` label.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Compilation will fail if both adin2111 and adin1100 are used
at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
On the interrupt handling, one thread per driver instance is involved
into monitoring the semaphor, sends inside the gpio callback triggered
by the gpio interrupt. Each time, when the link parameters are change,
the DM8806 is generating the gpio interrupt. After getting semaphor,
the application callback function which was linked during initialization
process is called to get the new link parameters with standard API
calls
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
New driver for Davicom DM8806 PHY. Driver is using standar mdio API
to manage the DM8806 switch controller. Register access needs the
PHY addres or switch address to be one of five possible values, since
DM8806 has built-in five PHY's. These values should be defined in the
application .dts file. One DM8806 ethernet port must corresponds with
one ethernet PHY node with two properties for ethernet port: one for
PHY address and one for switch address - <reg> for register access from
Internal PHY Register area and <reg-switch> for register access from
Switch Per-Port Registers area. Device tree example below:
example device-tree:
dm8806_phy: ethernet-phy@0 {
reg = <2>;
reg-switch = <8>;
compatible = "davicom,dm8806-phy";
status = "okay";
davicom,interface-type = "rmii";
reset-gpio = <&gpiod 2 GPIO_ACTIVE_LOW>;
interrupt-gpio = <&gpioc 1 GPIO_ACTIVE_HIGH>;
};
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
The ICS1894 phy AN_COMPLETE bit is latched high, this make the
BMSR first read return incorrect status of the AN state, update
one more BMSR read to ensure all latched bit is clear and BMSR
return actual status of the phy chip
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
I for the life of me do not know what is going on here with the RNB chip
but it seems this override must be set in order for the chip to work,
regardless of strap-in configuration, and if not set explicitly, the
value after a reset for these two bits will be seemingly random and
inconsistent. And it was working before by luck before removing a second
redundant reset in a recent commit, because apparently the register
was getting the opposite of the reset value according to the datasheet
which makes it work. The result of these bits after reset seem to vary
depending on host mcu, board, debugger, number of times reset, type of
reset, and with a pinch of random chance after keeping all variables
seemingly the same, so let's just set it to the value that works
explicitly, even if it doesn't make sense. The bit here doesn't have
clear documentation but it seems it's for using RMII regardless of the
strap in option, which is what we want to do anyways if we know the
interface type from DT, so I think it's fine, considering it is making
this driver work again.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
500 ms reset time is only for software reset and comes from IEEE spec.
Datasheet mentions for hardware reset the assertion of the signal should
only need to be 500 us, and 100 us after deassert to wait to access
programming interface.
Also remove an unused macro.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
No need to reset in cfg link, this was blocking system workqueue during
phy callbacks that call cfg link, since this happens from monitor work
handler which is in the system workqueue.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
the dts binding of the ethernet-phy has the option
"no-reset" and the according driver already has the
right logic to make use of it, but unfortunately
the connection between them was missing.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
In fixed-link mode, mdio remains unconfigured. This results in a null
pointer dereference, triggering a bus fault
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
The RGMII specifies output TXC/RXC and TXD/RXD without any clock skew.
Need to add skew on clock line to make sure the other side sample
right data. This can also be done in PCB traces.
This patch is to enable RGMII TX/RX delay to ensure timing.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Fix KSZ8081 binding properties:
- reset-gpios and interrupt-gpios are generally standard
properties and therefore should not be using a special name
- mc, is not the correct vendor prefix for microchip
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add driver for Realtek RTL8211F 10/100/1000M ethernet PHY.
This driver implements vendor specific behaviour like
detecting link state change by GPIO interrupt, which is not
present in the generic MII driver.
Fixes: #66348
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Add support for similar adin1100 phy, boath are 10Base-T1L,
only difference is that adin1100 connects through r/mii.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
Added changes required for nxp_enet ethernet driver to work
with multiple PHYs and fixed few problems:
- The cfg_link API resets PHY before configuring link. It was moved
here so the ethernet driver does not have to reset it - not all
PHYs need reset before configuring link and moving the reset code
here makes possible to have the reset done in a PHY specific way
(for example to reset by toggling GPIO pin). It also avoids ethernet
driver touching PHY registers without locking.
- When reset GPIO is not defined, reset is performed by setting reset
bit in control register.
- The cfg_link API does not return error when autonegotiation fails.
This fixes situation when the link is down at system start - ethernet
driver then skipped setting link-change callback and link was never
to be detected again.
- Added reset of excessive bits 16-31 when reading register values.
As only 16 bits are read from PHY, but the API is supposed to read
into uint32_t, the remaining bits contained previous data after
a successful read.
- Fixed missing mutex unlock when querying link state and link was down.
- Added missing initializer to link state variables. This could result
in link state change detection while link was still down, because
the speed/duplex settings could be random and old and new state
could be wrongly detected as different.
- Not logging link speed/duplex status when link is not up.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
- PHY can be set up as rmii but still use 25 MHz MDC, add DT property
value for this case
- Fix KSZ8081 driver spamming phy status in debug level logging,
and fix some other state/logging logic
- Fix PHY driver not rescheduling monitor work if first configuration
fails, change code path to use goto for errors
- Handle case where some phys are not using the gpio pins in phy driver
Make GPIO properties of ksz8081 phy optional since these hardware pins
may be unused on some boards
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
When there'is no phy at the address both registers will return
0xFFFF, giving a phy address of UINT32_MAX, not 0x00FFFFFF.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add Driver for KSZ8081 Ethernet PHY. The Generic MII Driver
is not sufficient to use for this PHY chip which has special
vendor implemented behaviors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Adds the tja1103 enet phy for setting phy options on the mr_canhubk3.
Co-authored-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Decouples the generic MII PHY driver from the adin2111 driver by making
it depend on an ethernet-phy compatible devicetree node rather than the
adin2111 driver not being enabled. This makes it possible to add the
adin2111 driver to tests/drivers/build_all/ethernet
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Updates Ethernet PHY devicetree bindings to be more consistent with
Linux by using the standard `reg` property for the PHY address instead
of a custom `address` property. As a result, MDIO controller bindings
now require standard `#address-cells` and `#size-cells` properties.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Add `mdio_read_c45()`/`mdio_write_c45()` APIs for Clause 45 access
and remove the `protocol` MDIO binding property so that MDIO bus
controller can support more than one protocol.
A new MDIO header is introduced with generic opcodes, MMD and
registers addresses, to be used by MDIO and PHY drivers.
Existing MDIO drivers that support both Clause 22 and Clause 45
access are migrated to the new APIs.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Now that all in-tree phys are declared under their mdio bus, drop the
`mdio` property and use DT_INST_BUS to find the bus.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add support for ADIN1110 10BASE-T1L Ethernet MAC-PHY.
The ADIN1110 is an ultra low power, single port, 10BASE-T1L
transceiver design for industrial Ethernet applications and is com-
pliant with the IEEE® 802.3cg-2019™ Ethernet standard for long
reach, 10 Mbps single pair Ethernet (SPE). Featuring an integrated
media access control (MAC) interface, the ADIN1110 enables direct
connectivity with a variety of host controllers via a 4-wire serial
peripheral interface (SPI). This SPI enables the use of lower power
processors without an integrated MAC, which provides for the
lowest overall system level power consumption. The SPI can be
configured to use the Open Alliance SPI protocol or a generic SPI
protocol.
Documentation:
https://www.analog.com/en/products/adin1110.html
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Adds PHY driver. Works via MDIO API and
exposed ADIN2111 MDIO Clause 45
functions.
Link status detection is triggered by
ADIN2111 driver within offloaded IRQ
handler.
Supports:
- LED0, LED1 enable/disable
- Fatal HW error detection
- AN 2.4V tx mode enable/disable
The initialization order is important.
PHY 2 must be initialized after PHY1.
Therefore, it shall be defined after the 1st one
in the devicetree.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Advertise Gigabit Ethernet if the PHY supports it. As with the
other speeds, it is assumed the PHY supports both duplex modes.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Just use dev->name. This change follow same principles applied when
DEV_CFG and DEV_DATA macros were removed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
A common pattern here was to take the work item as the subfield of a
containing object. But the contained field is not a k_work, it's a
k_work_delayable.
Things were working only because the work field was first, so the
pointers had the same value. Do things right and fix things to
produce correct code if/when that field ever moves within delayable.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
