Local register read/write functions have been removed and replaced
with calls to the new MFD functions.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
Add memory mapping to driver in order to use driver with platforms based
on Cortex A with enabled MMU.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Check the return value from gpio_add_callback() and fail driver
initialization if non-zero.
Fixes: #58584
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This makes Kconfig logging options for this driver depending on whether
the driver is enabled or not.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Basically, once a pin is configured for interrupt, we enable the latch
on it, in order not to miss short pulses.
The bottom half of the interrupt then reads the input port twice, to
read the latch and then read the potentially new state of the pins, to
compute the posedge, negedge, and level callbacks accordingly.
Signed-off-by: Vincent Geneves <vgeneves@kalray.eu>
When accessing GPIO by pin, access only the required port register
(instead of systematically accessing both PORT0 and PORT1).
Signed-off-by: Vincent Geneves <vgeneves@kalray.eu>
Clean up whitespace etc. using clang-format after previous changes. No
functional changes intended.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Added support for interrupt-driven GPIO for this driver if an interrupt
line is defined. Note that interrupt support is optional in the GPIO
core so it may or may not be present.
The core provides a single state change notification whenever any line
changes state on a given bank, so we need to check the states of the
lines ourselves to determine what has actually changed.
Also, the driver treats the first and second GPIO banks as mostly
separate devices, but a single interrupt is shared by both banks, so the
ISR ends up being registered by the first bank which also triggers
handling on the second bank if required.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The properties being read for the all-inputs and all-outputs flags in
the driver for the second GPIO channel did not match the ones listed in
the DT schema or the existing device tree files. Fix this.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Make sure MFD driver for nPM6001 gets built, and, that GPIO driver comes
later in the init sequence.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Status readback has been added in the latest silicon revision.
.port_get_raw and .port_toggle_bits are now supported
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
A glitch was observed if a GPIO PIN was configured to a
non-default state by ROM and then Zephyr programs the pin
for the same configuration. Root cause is GPIO hardware
implementing two output bits for each pin. The alternate
output bit is in the pin control register and is r/w by
default. The other bit exists in the GPIO parallel ouput
register and is read-only by default. The hardware actually
reflects the pin's output value into both bits. The fix is
to configure the pin with alternate output bit read-write
and the last step is to disable alternate output which
enabled read-write of the parallel bit. GPIO API's can
then use the GPIO parallel out registers. Add logic to
return an error from the GPIO interrupt configure API if
a pin is not configured as an input. Hardware only performs
interrupt detection if the input pad is enabled.
Hardware supports a pin being configured for both input
and output. Applications should add the GPIO_INPUT flag
to all pin configuration requiring interrupt detection.
The interpretation of input and output flags for the
get configuration API appears to be only one of the
flags can be set. Please refer to the GPIO driver tests.
Updated GPIO interrupt configure to clear the input pad
disable bit due to interrupt detection HW is connected
only to input side of pin.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add Port 14/15 to device tree. These ports can only be configured as input.
Error out in gpio driver if user sets them as output.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The iMX platform always uses pinctrl, there's no need to keep
extra macrology around pinctrl. Also updated driver's Kconfig to `select
PINCTRL`.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The MCUX platform always uses pinctrl, there's no need to keep extra
macrology around pinctrl. Also updated driver's Kconfig options to
`select PINCTRL` (note that some already did).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove all init functions that do nothing, and provide a `NULL` to
*DEVICE*DEFINE* macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
On iMX.RT devices, the number of GPIO pins exceeds the maximum of
64 that the PINT interrupt controller can support. Therefore, two
interrupt lines are now shared between the GPIO modules.
This patch allows the user to set the interrupt source for a GPIO
peripheral. For most LPC devices, this will always be the PINT. For some
RT devices, the PINT cannot use pins on GPIO modules other than 0 and 1
as input, and thus the INTA and INTB sources should be used.
Since Zephyr does not support sharing these interrupt between all GPIO
controllers, the user must configure a subset of all GPIO controllers to
use the shared module interrupts. An example of how to do so is provided
for the RT595 EVK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove PINT management code from the LPC GPIO driver, as this code is
now contained within the PINT interrupt controller driver, which exposes
an interface to install interrupt callbacks.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
1. Move the GPIO mux setting to the soc layer. The GPIO MUX
value may vary based on the SoC Family
2. Enable the digital input buffer if available
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Implement the driver method pin_interrupt_enable and pin_interrupt_disable.
This commit fixes getting the get_pending_int by updating the interrupts
field in the gpio_emul_data filed when interrupt is triggered. Also,
introduces a new filed enabled_interrupts to better simulate the
behavior of the interrupt pending and whether the interrupt is
enabled/disabled.
Signed-off-by: Sung-Chi Li <lschyi@google.com>
Add pin_interrupt_enable and pin_interrupt_disable in gpio_driver_api,
and add corresponding APIs in gpio.h for application to enable/disable
an interrupt without reconfiguring again.
This CL also Create a new Kconfig option for this feature.
Signed-off-by: Sung-Chi Li <lschyi@google.com>
We get compile warnings of the form:
error: converting the result of
'<<' to a boolean; did you mean
'((__aeabi_ctype_table_ + 1)[(byte)] << 28) != 0'?
[-Werror,-Wint-in-bool-context]
if (!isprint(byte)) {
^
Since isprint (and the other is* functions) return an int, change check
to an explicit test against the return value.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add config and data structs to the vnd,gpio test driver as these are
required by the GPIO API.
Fixes: #55884
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
remove all #ifdef CONFIG_SOC_SERIES_STM32xx
before to add a st,stm32g0-exti compatible
added to the matching targets:
C0/G0/U5/L5/MP1:
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
An interrupt is triggered for every edge, but only the desired edges cause
a callback to be called.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Should be the Output LATch register. "IK" is one key away from "OL" on
QWERTY keyboards.
This define wasn't actually used anywhere.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Port the gpio_keys_zephyr driver from the gpio subsystem with a
dedicated API to the input subsystem reporting input events.
Move the test as well, simplify the cases a bit since the API is simpler
now.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added initial version of Infineon CAT1 GPIO driver.
Added initial version of binding file for Infineon CAT1 GPIO driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Generalize the driver for PCAL6408A into a more abstract base
and reuse this abstraction to implement a driver for
PCAL6416A.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The interrupt status of the GPIO was not cleared when a new
interrupt configuration was set. This prevents the driver from
passsing all the gpio tests.
Fixes#54833
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Note: RP2040 can support single-ended IO, by setting the GPIO_OUT
register to a constant value, and then changing the GPIO_OE register
instead, when the output has to change. To do this, the output-setting
functions need to know which pins have been configured as single-ended,
and for that reason the data structure has been extended to include
this information.
Another change is the PR, is that setting of the pull-ups/pull-downs
now applies to both inputs and outputs as well. Previous solution was
wrong, because if the user wanted to set up an input with a pull
resistor enabled, and then reconfigure it to an output without any
pulls, then the pulls remained in place for the output. Now pulls
are correctly set based on the gpio flags for outputs too, and this
is especially useful for single-ended outputs too.
Signed-off-by: Purdea Andrei <andrei@purdea.ro>
Drop STM32 pinmux driver in favor of pinctrl. Some definitions located
in pinmux headers were used by the pinctrl driver, so they have been
moved there.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Since not all GPIOs support voltage selection, voltage flag
is only set if voltage selection register is present.
fixes: #54366
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
cy8c95xx I2C GPIO support was broken in commit 4b30008 due
to wrong i2c bus and addr were wrote during GPIO_PORT_INIT.
Now fix this issue.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
The driver currently stores num_keys in both config and data. Drop the
data copy, save 4 bytes of RAM.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The driver is missing the GPIO initialization entirely, meaning that
flags like PULL_UP are not currently being applied. Add the missing
call.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix two "unused variable" warnings when compiling with assertions
disabled. The two variables are used only in the __ASSERT() call.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add support for automatically configuring GPIO hogs defined in the
devicetree during system initialization.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add kscan pins gpio driver for KSI[7:0], KSO[15:0] pins that
they can be configured to gpio mode. These pins registers address,
bit fields and function are different from GPIO group, so I create
a new compatible driver for these pins.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Fix handling of gpio-reserved-ranges within MCUX iGPIO driver, to ensure
that the configuration IDX will be correctly calculated for pins where
multiple reserved ranges are present on the GPIO controller
Fixes#52506
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
If the bootloader changes iof_en/iof_sel settings before zephyr launching,
GPIO does not behave correctly.
These values should be 0 initially, Initialize to 0 at GPIO initialize.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
peripheral-id property should be eventually removed entirely.
For now set it as optional and allow skipping the usage
in GPIO driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Common GPIO driver needs to be initialized before e.g UART driver
to ensure correct GPIO clock configuration when configuring UART pinout
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.
Enable nocache in each driver use it.
Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
Change Summary:
Update Base addr to set direction to use Aligned IP base address instead
of Port Base Address. Port Base Address + offset to direction register
will set incorrect value for Port B,C & D. For ex: In cases when more than
1 port is configured on the same IP, the DTS node for port B will start
at offset 0xC. Calculating the port using Port Base will yield offset of
PORTB DIR register which is at offset 0x10 from Aligned Base, and as a
result will result in setting DIR register of PORTC instead.
Signed-off-by: Ravik Hasija <ravikh@fb.com>
Change Summary:
Moving the setting of Pin direction before setting/clearing the pin
configured as output for the change to correctly take place.
Signed-off-by: Ravik Hasija <ravikh@fb.com>
`spi_is_ready` function is being deprecated in favor of
`spi_is_ready_dt` so let's replace the old usage in the tree.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
This commit adds support for get_config and get_direction functions
for the nct38xx IO expander family.
Also applies the clang-format changes.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
This commit fixes the comment and adds the missing assignment of
return value from i2c read byte command in the nct38xx driver.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
In npcx ec series, two detection levels, 3.3V (default) and 1.8V are
supported during gpio configuration. But the current implementation
always selects default detection level whether NPCX_GPIO_VOLTAGE_1P8 is
set. This PR is a fix for this issue.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
RT1718S is an i2c-based TCPC chip that supports 3 additional GPIOs.
The pins can be used for USB-C operations e.g. handling FRS, but they
can also work as usual GPIOs.
Add a driver for the RT1718S GPIO and a handler for an alert signal from
the chip. The handler reads the alert register once asserted and calls
the GPIO interrupt handler if needed(Vendor-defined alert).
gpio_rt1718s.c file and "richtek,rt1718s" node collect common properties
and data for all RS1718S functionalities. The file can be extended for
TCPC driver. rt1718s.h file also defines inline functions with i2c
operations common for all drivers. The common header and source files
can be moved to tcpc directories once the tcpc driver is added since it
is the main functionality.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
`struct device::config` is a `const void *`, so this struct does not need
to be mutable.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Parts of the macro used `inst`, others `n` for the instance number; only
`n` was actually defined (so `inst` expanded to the empty string, causing
name errors with more than one instance).
Unify everything to `inst`.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The NPCX driver did use deprecated voltage macros. Define vendor
specific flags instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The pin get function was using deprecated macros. Note that the set
implementation already uses vendor specific flags.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fixed how data is read in mcp23sxx_read_port_regs
The data is now stored in an array to get the
actual data from spi
Signed-off-by: Daniel Skatt <daniel.skatt@gmail.com>
Add support input interrupts for GPIO pins on NXP S32Z27
SoC. The driver will convert GPIO pin to respective
interrupt line that will be processed by External
Interrupt Controller.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Zephyr implementation is limited to 4 IRQ per GPIO bank when up to 8 is
theoritically possible.
It is now possible to use until 8 IRQ per GPIO bank. This can be
achieved with minimal effort in a device tree overlay:
&gpio0 {
interrupts = <4 2>,<5 2>,<6 2>,<7 2>,<32 2>,<33 2>;
};
&gpio1 {
interrupts = <34 2>,<35 2>;
};
Signed-off-by: Guy Morand <guy.morand@bytesatwork.ch>
Fix the enabling of the independant IO supply.
Function LL_PWR_EnableVddIO2 is called LL_PWR_EnableVDDIO2 on U5.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Adds open drain support to atmel,sam-gpio drivers, by writing to the
PIO_MDER or PIO_MDDR registers during gpio configure.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Implement GPIO driver minimal API's for NXP S32 devices, based on SIUL2
peripheral. SIUL2 allows to control the pins electrical characteristics
such as internal pull resistors, pin direction and more.
GPIO driver API's for interrupts will be implemented in a future patch.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Register definition header was missing, SoC common header as well (for
ite_intc_get_irq_num).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some SoCs define stuff in soc.h, used in drivers or SoC code. Note that
soc.h is not introduced here as a catch-all header. soc.h optimizations
or removal is out of the scope of this patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Previous commit removed pinmux from the platform but neglected to
remove the dependency in this Kconfig resulting in build failures
when target application configures GPIO support.
Fixes#51144
Signed-off-by: David Leach <david.leach@nxp.com>
Clean up and refactor x86 SoC headers in preparation of adding
new platforms in the future.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
gpio_manage_callback() returns -EINVAL if it could not remove
callback. However if the list is empty success is returned when trying
to remove callback.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This commit adds a driver to simulate GPIO state and interrupts
using the keyboard when using SDL.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Input pins in ESP32 (34 to 39) have no pull-up / pull-down internally.
Current behavior is that gpio driver fails when "disabling it", which
should not happen. It need to fail only when enabling this feature.
Fixes#50615
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add code to handle parsing the gpio-reserved-ranges property present on
iMX GPIO controllers, so that gpio controllers with gaps in their pin
indexing can still have pinmux settings applied correctly.
Fixes#50142
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In STM32U5 as well it is required to enable VDD before use.
Difference is that U5 enables this under PWR_SVMCR_IO2SV flag.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add BUILD_ASSERT to check max val of ngpios. If someone sets ngpios to
more than 32, and acts on pin 32 or higher, memory corruption will
result. This is only a problem with the emulator, real hardware
will have limits that are probably much smaller.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
PR #49550 missed adding proper RTCIO pin mapping
in a few rtcio functions calls, which causes board
to crash. This fixes it.
Closes#50238
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Use the clock control API to enable peripheral clocks. Note that both
GPIO and pinctrl drivers are updated at once since they share some IP
blocks.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This adds GPIO driver for Renesas SmartBond(tm) family.
Driver supports pin configuration (input/output) and interrupts on edge.
Interrupts on level are not supported by hardware.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Simplify driver by using DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP (avoids
DT_DRV_INST and auxiliary macro).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Simplify driver by using DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP (avoids
both DT_DRV_INST and auxiliary macro).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Current implementation misses disabling input/output mux
once GPIO has already been configured. It means that after 1st
configuration, if GPIO is reconfigured, it won't disable previous
definitions, causing unexpected behavior.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Change Summary:
- Updating GPIO_CFG_IRQ define to enable multiple interrupts to
accomodate for IP configuration where each pin when interrupted
can trigger CPU interrupt.
- Removing gpio_dw_unmask_int define as it is NO OP
Signed-off-by: Ravik Hasija <ravikh@fb.com>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Recent change to constify struct devices pointers introduced a
compile warning in gpio_xlnx_ps driver. Update driver to fix a
case that got missed in the constification that fixes the warning.
Signed-off-by: Kumar Gala <galak@kernel.org>
It is frequent to find variable definitions like this:
```c
static const struct device *dev = DEVICE_DT_GET(...)
```
That is, module level variables that are statically initialized with a
device reference. Such value is, in most cases, never changed meaning
the variable can also be declared as const (immutable). This patch
constifies all such cases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove redundant declarations by definining and initializing before
variables are used.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move gpio_cmsdk_ahb.h out of drivers/gpio and into include/drivers/gpio.
This is used by few board files so it should be in include.
This allows to remove few odd
"zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)".
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
gpio_utils.h header relied on other files including its dependencies.
This patch adds all necessary includes to make it self-contained.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The stm32F1x serie does not provide the pin_get_config function,
Even if the CONFIG_GPIO_GET_CONFIG is set, the -ENOSYS error code
is returned by the z_impl_gpio_pin_get_config().
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Define a pin structure to carry the pin configuration elements
such as push/pull, opendrain, input/output, high/low.
This structure will give the gpio_flags_t to the gpio_stm32_get_config.
Only the stm32F1x serie does not provide the pin config get function.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In the stm32 gpio driver, the gpio_stm32_get_config function
also returns the pin state HIGH or LOW) to match gpio_pin_get_config
This is valid with CONFIG_GPIO_GET_CONFIG.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This PR fixes up a race condition which could cause GPIO writes to be
dropped when one thread was toggling a gpio on a port, and a different
thread was also modifying a (different) gpio on the same port.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Add the "zephyr/" prefix to various #include statements that are
preventing the CI form running with LEGACY_INCLUDE_PATH=n.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)
Use `do { ... } while (false)' instead of `do { ... } while (0)'.
Use comparisons with zero instead of implicitly testing integers.
The commit is a subset of the original auditable-branch commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a
Signed-off-by: Simon Hein <SHein@baumer.com>
In update the Kconfig to depend on devicetree, the SAM4L
driver was missing a 'default y'.
Also remove unnecessary 'depends on GPIO'.
Signed-off-by: Kumar Gala <galak@kernel.org>
Inside gpio_nrfx_pin_interrupt_configure, the "ch" variable is allocated
inside the "if", but then it gets dereferenced and the pointer saved in
trigger_config, which is used in the outer context.
This works fine right now, but that memory location could possibly be
reused by another automatic variable if the code gets changed.
Moving it in the function context to avoid any potential problem.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Update gpio drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
We remove 'depend on' Kconfig for symbols that would be implied by
the devicetree node existing.
Signed-off-by: Kumar Gala <galak@kernel.org>
This CL configures low-voltage (1.8V) detection via GPIO driver with
GPIO_VOLTAGE_1P8 flag. It also adds support for this flag in
pin_get_config() function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Cleanup npcx low-voltage (1.8V) detection configuration. It removes
unused soc utilities, macros, and DT node. We will configure this
feature by GPIO driver with GPIO_VOLTAGE_1P8 flag later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add simple clock control node in devicetree for beetle to handle
relationship between drivers (uart, timers, gpio) and clock controller
device.
Signed-off-by: Kumar Gala <galak@kernel.org>
Use DT_INST_FOREACH_STATUS_OKAY to reduce duplicated code for each
instance.
We make interrupts optional since they aren't always available.
Signed-off-by: Kumar Gala <galak@kernel.org>
Remove Kconfig symbols that determine which instances and just use
the number of enabled instance in the devicetree to determine which
instances to build.
Signed-off-by: Kumar Gala <galak@kernel.org>
Remove dead clock gate code and associated PM code as the platforms
that used the clock gate code are no longer supported in Zephyr.
Signed-off-by: Kumar Gala <galak@kernel.org>
The shared IRQ code has been broken for several releases and no one
seems to have noticed. The platforms that this was used on are not
supported in Zephyr anymore so remove the code.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add gpio_pin_get_config function to gpio_driver_api.
This function is used to read current configuration of pin.
The gpio_pin_get_config checks if driver implements this function and
returns -ENOSYS if it isn't implemented.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Now that we have 8 bits reserved for vendor specific GPIO flags,
introduce a new set of flags for nRF platforms to configure pins drive
mode. These new flags are equivalent to the previous existing ones, but
use a naming scheme the fits better with vendor hardware capabilities.
The table below shows the equivalence between old and new flag
| Old flags | New flags |
|---------------------------|-----------------------|
| `NRF_GPIO_DS_DFLT_LOW` | `NRF_GPIO_DRIVE_S0` |
| `NRF_GPIO_DS_DFLT_HIGH` | `NRF_GPIO_DRIVE_S1` |
| `NRF_GPIO_DS_ALT_LOW` | `NRF_GPIO_DRIVE_H0` |
| `NRF_GPIO_DS_ALT_HIGH` | `NRF_GPIO_DRIVE_H1` |
| `NRF_GPIO_DS_DFLT` | `NRF_GPIO_DRIVE_S0S1` |
| `NRF_GPIO_DS_ALT` | `NRF_GPIO_DRIVE_H0H1` |
| `NRF_GPIO_DS_DFLT_LOW \|` | `NRF_GPIO_DRIVE_S0H1` |
| `NRF_GPIO_DS_ALT_HIGH` | |
| `NRF_GPIO_DS_ALT_LOW \|` | `NRF_GPIO_DRIVE_H0S1` |
| `NRF_GPIO_DS_DFLT_HIGH` | |
Documentation has been written to explain in more detail the meaning of
the flags and how they can be used.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The naming of the custom DS flags is not clear for nRF platforms. This
patch removes all the NRF_GPIO_DS* flags. New flags will be
re-introduced in a follow-up commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In npcx series, not all GPIO pads support Multi-Input Wake-Up Unit
(MIWU) functionality. Hence, this CL adds checking whether GPIO's pad
configuration is valid first before using it.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The TI SimpleLink SDK got updated to version '4.40.04.04' in 'hal_ti'.
This introduced renames of some functions in HAL and has to be reflected
in Zephyr drivers which make use of them.
This renames 'PRCMPowerDomainStatus' to 'PRCMPowerDomainsAllOn' in all
affected 'cc13xx_cc26xx' drivers.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In prepration for configuring I2C/SPI defaults at the board level,
change the DesignWare GPIO driver's clock gate option to depend on clock
control instead of selecting clock control. This breaks a Kconfig
dependency loop when adding the following to a board's
Kconfig.defconfig:
config SPI
default y if SENSOR
There aren't any in-tree users that enable the clock gate option, so
there aren't any places in-tree that now need to enable the clock
control driver. Out-of-tree users that set CONFIG_GPIO_DW_CLOCK_GATE=y
will now also need to set CONFIG_CLOCK_CONTROL=y.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
if ISR is called for an event on pin X but
another event occurs on pin Y in between the call
to GetStatus() and ClrStatus(), pin Y event wil get
cleared without being processed
Signed-off-by: Maxim Adelman <imax@fb.com>
The driver returns -EIO when a pin to be disconnected was not earlier
configured as input or output, what is not in line with the GPIO API.
This commit changes the driver to return 0 in such case.
Also -EIO is incorrectly returned when an interrupt trigger cannot be
configured in the nrfx_gpiote driver. This commit corrects this value
to -EINVAL.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Some services require the ability to query whether a GPIO pin
is configured as an input, output, both, or neither prior to
performing any operations at the service level. This is done
in order to reduce state tracking within the service.
To that end, this change adds
* `gpio_port_get_direction()`
* `gpio_pin_is_input()`, and
* `gpio_pin_is_output()`
Signed-off-by: Christopher Friedt <cfriedt@fb.com>
Stop relying on <soc.h> to access HAL APIs. Use generic, per-API headers
instead. Note that <soc.h> has been left as is for now, since ARM MPU
relies on a fragile chain of includes/type definitions.
This change should improve compilation efficiency, as we no longer pull
APIs that are not needed. A similar approach is followed by STM32
drivers.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit drops the `IRAM_ATTR` macro from the function declarations
because:
1. `IRAM_ATTR` macro makes use of the `__COUNTER__` preprocessor macro,
which increments for every macro invocation and causes the section
specified in the forward declaration to not match that of the
function definition.
2. Section attributes need not be specified for forward declarations.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
All the gpio drivers are based on devicetree and thus we always set
HAS_DTS_GPIO, thus we don't need this Kconfig option anymore. Remove
uses as its safe to assume DTS is supported for GPIO.
Signed-off-by: Kumar Gala <galak@kernel.org>
Remove unconditional write to PCA95xx output registers in setup_pin_dir,
and only write to output registers if selected pin is configured as
an output.
Fixes#45774
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
some iMX RT SOCs have non contiguous sets of gpio pins available, which
caused issues when selecting appropriate pinmux for these parts. Add
workaround code to adjust offset of pinmux settings when configuring
these pins.
Fixes#44391
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Incorrect GPIOTE channel was being freed because the pin number
being used is not the absolute pin but the pin within the port.
Signed-off-by: Wael Barakat <waelsbarakat@gmail.com>
Add pin control support to gpio_imx driver, so that GPIO pin muxes will
be selected when the use configures a pin as GPIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add additional pin controller settings for iMX application core SOCs, as
well as a "fallback" pin control setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
A missing semicolon caused compiler errors when more than one emulated
gpio device was defined in the device tree.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
switch gpio driver to use pio nodes to configure pin control settings,
and stop using pinmux driver within gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Set the PCR[MUX] field to kPORT_MuxAsGpio as part of configuring a GPIO
pin. This removes the need to explicitly call pinmux_pin_set() in board
code.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
add support for setting pinmux when using IOPCTL peripheral, as well as
setting pin configuration properties.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Introduce has-interrupt-mask-reg DTS property for nxp,pca95xx driver.
This additionnal property allow to specify that the gpio expander has an
interrupt mask register that must be configured by the driver.
This allow to use this driver with PCAL95xx.
This fixes issue #44834.
Signed-off-by: Xavier Chapron <xavier.chapron@stimio.fr>
Based on introduction of plain GPIO configurations in STM32 pinctrl
bindings, update STM32 pinctrl/gpio drivers to make this functionality
available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before updating stm32 pinctrl/gpio drivers to support plain GPIO
feature, rework pin configuration functions headers to provide
more clarity on the arguments and the information they convey:
- pin configuration
- pin function
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order for pinctrl support to be complete, RT series GPIO driver must
support pinmuxing within the driver level. RT series pinmux settings do
not correspond directly to gpio port/pin numbers, so use DTS mappings to
pinctrl nodes to select and apply pinmux settings in the gpio driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move the `pm_device_runtime_init_*` functions from <pm/device_runtime.h>
to <pm/device.h>. The initial device state should be settable
independently of whether `CONFIG_PM_DEVICE_RUNTIME` is enabled.
This also resolves a compilation error when attempting to use these
functions without also including <pm/device.h>.
Function documentation is also updated to be more general than only
referencing runtime PM, as this also applies to system PM and manually
run actions.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Re-running the script that checks for the const qualifier missing on
struct device ISR's parameter.
The script also changes the parameter 'arg' to 'dev' when relevant.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The Serial Wire JTAG configuration is moved to
F1 pinctrl DTS.
The configuration in GPIO didn't apply to the
majority of the STM MCUs except F1.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
I introduced some errors during the gpio_dt_spec/i2c_dt_spec conversion
process. This patch fixes the issues so that driver builds.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Driver implementation for the Xilinx Processor System MIO / EMIO GPIO
controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs.
The driver is split up into source and header for a parent controller
device and source and header for 1..n child GPIO pin bank devices.
The parent device driver takes care of IRQ handling, the GPIO pin bank
driver provides pin / bank access according to the API defined by the
GPIO subsystem.
More than one device for this type of GPIO controller is required as
it provides access to a number of GPIO pins well in excess of the 32
pins addressable by the current GPIO API (whereever parameters or
return values come in the form of a bit mask):
- Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks.
- ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Reserve the upper 8 bits of gpio_dt_flags_t for SoC specific flags and
move the non-standard, hardware-specific GPIO devicetree flags (IO
voltage level, drive strength, debounce filter) from the generic
dt-bindings/gpio/gpio.h header to SoC specific dt-bindings headers.
Some of the SoC specific dt-bindings flags take up more bits than
necessary in order to retain backwards compatibility with the deprecated
GPIO flags. The width of these fields can be reduced/optimized once the
deprecated flags are removed.
Remove hardcoded use of GPIO_INT_DEBOUNCE in GPIO client drivers. This
flag can now be set in the devicetree for boards/SoCs with debounce
filter support. The SoC specific debounce flags have had the _INT part
of their name removed since these flag must be passed to
gpio_pin_configure(), not gpio_pin_interrupt_configure().
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Ignore the flag instead of rejecting it with -ENOTSUP, as this is what
the GPIO API expects from drivers that do not support debouncing.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
fix incorrect gpio driver struct used in driver data.
This should not have caused any issue as currently
sizeof(gpio_driver_data) == sizeof(gpio_driver_config).
Signed-off-by: Simon Frank <simon.frank@lohmega.com>
Properly set both pull up and down flags explicitly when
making changes.
Properly implement disabling interrupts on a given pin.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
The current MCUX IGPIO driver assumes that the target SoC supports
the DR_SET, DR_CLEAR, and DR_TOGGLE functionality, but some do not
(namely, the M7 core of the i.MX8M Plus SoC). Current releases of
the MCUXpresso SDK IGPIO driver contain utility functions to set,
clear, and toggle pins which include provisions to support SoCs
with and without DR_SET, DR_CLEAR, and DR_TOGGLE, and this change
switches to using these utility functions.
Additionally, this change enables GPIO support on the mimx8ml8_m7
target.
Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
As a complement of 7689abee34,
which fixed an issue where gpio number could errouneously be
set to a number greater than 32 in DTS, there is also another
situation where driver instance can be configured with a pin number
greater than 32.
This PR adds another check in GPIO driver to confirm
whether the PIN number is within valid bounds.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Follows #41918.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This patch adds GPIO and 96board LS (Low Speed)iexpansion connector
support for SiFive HiFive Unleashed and also enables GPIO basic test.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
ESP32 has 2 GPIOs: gpio0 and gpio1.
Zephyr DTS model requires pin definition in dts file
from 0 to 31, meaning that when some pin within gpio1 range
is required, gpio driver needs to increament this value
by 32, required by LL API.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This corrects the following:
1. The priority of type cast is lower than member access. So don't need
the redundant parentheses.
2. The macro should be added to the parentheses.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Current gpio and uart initialization level is set to
PRE_KERNEL_2, which won't let uart_console subsystem
to init its hook properly as it has same level.
Prioritize uart and gpio so that the console hooks
are properly initialized.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
After #41918, build started to warn discard qualifer
in config struct. This adds const into those structs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fixed#41945
NO_PINT_INT can have the same value as a specific pin.
E.G. For 1 byte pint_pin_int_t it equaled interrupt1.
Now is instead always 1 higher than the highest pin.
Expects fsl to keep setting values from 0 to
(number of connected outputs - 1)
Signed-off-by: Martin Koehler <koehler@metratec.com>
Some drivers explicitely casted data/config from void * to the
corresponding type. However, this is unnecessary and, in many drivers it
has been misused to drop const qualifier (refer to previous commits).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to align with macros used to obtain a device reference (e.g.
DEVICE_DT_GET), align the PM macros to use "GET" instead of "REF". This
change should have low impact since no official release has gone out yet
with the "REF" macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The SAM spi driver depends on GPIO driver to work. It seems that this
dependency chain it is not handled. This select GPIO driver when SPI
driver is enabled. It rework GPIO and SPI Kconfig to select driver by
devicetree and drop entries at Kconfig.defconfig.series file.
Fixes#41525
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
GPIOTE channel was not freed when pin was reconfigured. This lead to
channel pool draining when pin was frequently reconfigured.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Enable the emulated GPIO driver by default if instances exist in
devicetree. This removes the need to manually enable `CONFIG_GPIO_EMUL`
when `CONFIG_GPIO` is enabled.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add GPIO driver for Gigadevice SoCs. The driver supports devices with
the AF and AFIO models.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a dummy driver for the `vnd,gpio` compatible to allow compilation of
drivers utilising GPIO when running "build_all" tests.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
SYS_INIT can be used for the same purpose, what is being run is simply
an initialization hook.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
i2c_burst_write can have portability issues with certain i2c
peripherals that can fail when this api is called. This fixes the case
where this can be easily replaced with i2c_write in mcp230xx,
pca95xx, stmpe1600, max17055, and tmp112.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
So far driver was using SENSE mechanism for all or none edge
interrupts. This was not convenient since in some modules may
require IN event to be used and other did not. Converting it to
use a mask specified in the device tree. Pins indicated in the
mask will use sensing.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Replace usages of DT_PARENT(DT_DRV_INST(idx)) with more idiomatic
DT_INST_PARENT(idx).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Call `gpio_stm32_clock_request` unconditionally with "true" if no
runtime PM is enabled, "false" otherwise. In case the GPIO was enabled
(e.g. by a bootloader), the device will be left in proper state when
runtime PM is enabled.
Also added pm_device_runtime_init_suspended to indicate that device is
in a suspended state (will prevent pm_device_runtime_enable to suspend
the device again).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The function is only used by the driver itself. This likely comes from
pre-runtime PM API usage.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Make gpio32_stm32_configure use runtime PM API (so that it can be used
externally without further effort). The raw version of the function (no
PM put/get) has been introduced for internal use.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The suspend operation for this device is a clock gating operation (i.e.
fast), so use synchronous put to skip unnecessary overhead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PM runtime API (get/put) provides an inline implementation when not
built-in. Such implementation always returns 1, so it is safe to not
guard PM runtime calls and check for < 0.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Change the function pm_device_runtime_enable() to return 0 on
success or an error code in case of error.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
PRE_KERNEL_1 is to be used for devices that have no dependencies
and do not use kernel features, such as those that rely solely on
hardware present in the processor/SOC. This commit updates these
gpios to initialize during the PRE_KERNEL_1 rather than the
POST_KERNEL. Some SoC drivers are moved to PRE_KERNEL_2 due
to dependencies.
A lot of 'other' drivers can depend on GPIOs though phandles
(such as reset lines, data or command gpios, etc...). Most of these
drivers that would need this would come up on the POST_KERNEL,
and it's likely the driver may not be up yet as it should be defined.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
The warning below appears once -Waddress-of-packed-mem is enabled:
/__w/zephyr/zephyr/drivers/gpio/gpio_sx1509b.c: In function
'port_write':
/__w/zephyr/zephyr/drivers/gpio/gpio_sx1509b.c:456:19: error: taking
address of packed member of 'struct sx1509b_pin_state' may result in an
unaligned pointer value [-Werror=address-of-packed-member]
456 | uint16_t *outp = &drv_data->pin_state.data;
To avoid the warning, use an intermediate void * variable.
More info in #16587.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
this allows using a pin numbering scheme as per Espressif's
documentation and HAL usage, where pin counting does not wrap
up when reaching a given number.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Refactor the mcp230xx driver to generically also support
SPI IO expanders, renaming it to mcp23xxx in the process.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
In #40140, all on-chip gpios where made to use `CONFIG_GPIO_INIT_PRIORITY`.
The lmp90xxx and sx1509b are off-chip gpios. This commit reverts those
changes for these two devices.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
The device PM subsystem _depends_ on device, not vice-versa. Devices
only hold a reference to struct pm_device now, and initialize this
reference with the value provided in Z_DEVICE_DEFINE. This requirement
can be solved with a forward struct declaration, meaning there is no
need to include device PM headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Make nrfx GPIO driver part of the PRE_KERNEL_1 initialization stage. As
a result, the GPIO driver can now be initialized before UART if
required, a device that is also initialized during PRE_KERNEL_1.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Change gpio_emul_input_set_masked_pend to log when it returns an error.
Changed all calls to gpio_emul_input_set_masked* to check the return
value.
Changed the function gpio_emul_input_set_masked_pend to apply the mask
to the provided values and not return an error if there are excess
values. In almost every call to that function, the value wasn't being
limited to bits set in the mask, so they were failing if there was more
than one gpio configured for INPUT|OUTPUT with a value of 1.
Fixes#40646
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Port some drivers to the recently introduced macros to showcase its
usage and be able to do some initial testing (nRF52840).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The macro already mentions in the docstrings that PM is not supported:
"Invokes DEVICE_DEFINE() with no power management support".
This patch removed the PM entry from the macro and ajusts its uses.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
For port_set_bits_raw(), port_clear_bits_raw(), and port_toggle_bits(),
the second parameter sould be gpio_port_pins_t type. Currently, it
doesn't have other side effect, but it sould be fix. This commit fixes
it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Refactors all of the on-chip GPIO drivers to use a shared driver class
initialization priority configuration, CONFIG_GPIO_INIT_PRIORITY, to
allow configuring GPIO drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_DEFAULT or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
Driver-specific options for off-chip I2C- or SPI-based GPIO drivers are
left intact because they often need to be initialized at a different
priority than on-chip GPIO drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Introduce combined GPIO drive strength flags for GPIO controllers only
supporting either default or alternative drive strength regardless if
the pin is driven to a high or a low level.
Fixes: #30329
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The PM callback is no longer referenced as "pm_control" but
"pm_action_cb", so reflect this new naming on the callbacks.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to have Espressif SoCs working with
the same uart drivers, all low level functions
are now replaced to hal_espressif HAL calls.
This also changes pinmux, gpio and uart
init order to meet its dependencies.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
