When attaching a device, it should look up if the dynamic addr is
already attached only, and not by the static addr.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The ENTDAA does not have a way to assign DA that are with a PID. It will
assign DAs that were in it's RRs in the order that they win arbitration.
Assign only available addresses in to it's RRs before ENTDAA.
Cleanup the attach api to no longer require a addr argument and remove
the helper function `i3c_determine_default_addr`. This now looks at if
it has a static address or if it already has a dynamic address (such as
from DEFTGTS) and will register the address if either exist with
precidence of dynamic addr over static addr.
This also fixes up the look up for if a device already has a dynamic
addr to find which pos of the RRs is it is in.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Fix M1 errors seen with HDR-DDR writes, M1 errors we seen between CRC
and HDR exit sequence. The fix was to set Bit-8 of HDR-DDR CRC TXFIFO
word.
Signed-off-by: Naveen Gangadharan <naveeng1001@meta.com>
Some IBI TIR packets can be larger than the ibi data fifo size
which can prevent it from receiving the full packet. This adds
a data struct in to the driver data where data can be pushed
to as data is being transfered.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add i3c_bus_for_each_i3cdev and i3c_bus_for_each_i2cdev to more easily
iterate through each i3c or i2c device on the bus.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Cadence I3C target FIFO width has been increased to 4 bytes in i3c
hardware REV_ID 1.7. Writing 1 byte to 4 byte FIFOs can cause
unintentional padding for bytes written from TX threshold interrupt
handler. Fixed the target callback to handle tx width of i3c target
writes to FIFO, by using run time rev_id check.
Signed-off-by: Naveen Gangadharan <naveeng1001@meta.com>
Fixing a bug where during the bus_init routine, when a slave is
initialized, the target hardware can get an interrupt, and this can occur
before the target_config structure is assigned; the generic IRQ handler
attempts to use this structure to grab callback function pointers, but
with no target config it attempts to access the structure member from a
null pointer. Fix works by adding ternary operation during IRQ that first
checks if target_config is null or not.
Signed-off-by: Matthew Mulloy Steinborn <mulloystmatthew@meta.com>
Adjusting T_sco is only support by revision 1p4 and above. Also,
correct the T_sco default time from 10ns to 8ns.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Revision 1p7 of the silicon added support for IBI TIR, full word fifo
while target usage, defining byte with direct CCCs. This also adds
support of HDR-DDR.
This also fixes short ccc commands where multiple targets in a
payload for the same ccc.
Modification of the i3c_target_tx_write had to be done in order to
distinguish the difference for each fifo to be written to.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The CDNS will report a M0 error if the data length is not what
it expects, but certain CCCs can have a variable length such as
GETMXDS and GETCAPS. This sets it up to ignore the M0 error if
it sees that ccc was GETMXDS or GETCAPS.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Some targets do not give EoD at the end of a register read. They will
auto increment their address pointer on to the next address, but that
may not be of interest to the application where the buffer size will
only be set to the size of only that register. If the target, does
not give an EoD, then the Controller will give an Abort... but this
should not be treated as an error in this case.
There is still however a case where an abort Error shall still be
considered as an error. Athough the driver does not support it yet,
threshold interrupts are to be used if the length of the buffer
exceeds the size of the fifo. There could be the case where the
cpu can not get around fast enough to pop out data out of the rx
fifo and it will fill up. The controller will just give an abort
as it can not take any more data.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The command response buffer will return the total number of bytes
transfered. This will write back to the pointer which is to contain
the number of bytes sent or received.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This renames the I2C 'DCR' mode to 'LVR' as that is the variable it
should be looking at and not the dcr value. This also fixes the get
'lvr' mode argument.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Previously, the idle bit would be read for X amount of times. This
could vary alot depend on the CPU speed. Timeout is now to happen
from the cycle time.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
For example, if a driver needed to reserve address before it does a
ENTDAA, it would need to get free address in a loop, but the get
free address func would return the same address everytime. It needs
the start address, which would be the last free address it go, to
be passed in to get the next free address.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The Cadence I3C was not building with CONFIG_I3C_USE_IBI, this fixes
the build and will give a small code size reduction when enabled.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
If a transfer happen in rapid sucession. It was possible for
the core to not be ready to accept another command. Poll on
the idle status bit until the core is ready to accept new data.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Due to a bug, after a completed transfer happen. Only the first
command response error was read. This fixes the issue so all
commands are read for if an error occurred.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
When a controller is running at full SDR speed at 12.5MHz, there needs
to be enough time for the processor get around to writing more data in
the fifo. Previously at -1 the size, this was enough for 1MHz with a
decent processor, but not enough at a 12.5MHz SCL.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The cadence i3c ip requires it's retaining registers to be updated
when a device is detached or attached.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This adds the reattach api necessary for writing the i3c retaining
registers within the cdns i3c when the dynamic address changes.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
