Commit graph

4 commits

Author SHA1 Message Date
Ioannis Karachalios
7c5c459440 drivers: memc: Fix various APS6404 device issues
This commit deals with fixing various issues that prevents
the device from being built. In specific:

1. Fix default timing macro definitions to build with
an MSPI controller, other than AMBIG.
Add macro definition for MSPI_PORT.
2. Timing settings should be applied only when MSPI_TIMING
is defined. Otherwise, the APS6404 initialization routine
will fail with -EIO.
3. Similarly, use MSPI_XIP and MSPI_SCRAMBLE to apply XIP
and SCRAMBLE device settings, respectively (optimization).
4. MEMC_INIT_PRIORITY is assigned higher priority than
MSPI_INIT_PRIORITY which results in compiler error as
APS6404 device initialization depends on its underlying
MSPI bus controller.
5. The 'acquire' subroutine should be compiled when PM_DEVICE
is used (suppress compiler warning).

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
2024-11-08 13:56:31 -06:00
Pisit Sawangvonganan
1bcae0ea9f style: drivers: comply with MISRA C:2012 Rule 15.6
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
2024-08-20 10:33:51 +02:00
Richard Wheatley
188fc58c72 drivers: update AMBIQ drivers to use proper base address
REG_X_BASEADDR will be removed from all hal files.
This forces the use of the peripheral base address
Define MSPI_PORT macro for chip drivers

Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
2024-08-11 19:18:09 -05:00
Swift Tian
c7ed0b6aa8 drivers: memc: Add APS6404L device driver
The APS6404L psram is a quad SDR SPI device that runs up to 100MHz.
It can provide 8MB of external RAM for SoCs that supports XIP feature.
The device driver uses MSPI bus API and could be used across
different controllers that implement the MSPI bus API.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2024-06-14 21:07:00 -04:00