Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add power management support for Apollo3/Apollo3P UART, and
automatically enables device runtime power management
Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
Remove address-of operator ('&') when assigning `init_fn`
function pointer in `DEVICE_DT_INST_DEFINE` macro.
This change aims to maintain consistency among the drivers in
`drivers/serial`, ensuring that all function pointer assignments
follow the same pattern.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
If a clock control device is set in the `clocks` property,
it is used to determine the frequency.
If `fixed-clock` is set for the clocks, we use that value as is.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Introduce the `COMPAT_SPECIFIC_...` macros to determine the function name
from the compatible name.
These macros allow the isolation of device-dependent code in a generic way.
For example, if the compatible name is `ambiq,uart`,
The `COMPAT_SPECIFIC_DEFINE` macro is replaced by `AMBIQ_UART_DEFINE`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
UART controller present in Ambiq SoCs is mostly compatible with PL011, but
requires some quirks that are implemented in this commit:
- the peripheral needs to be powered on first, via the PWRCTRL core,
- peripheral clock needs to be enabled and configured via the CLKEN/CLKSEL.
registers.
The quirks mechanism was inspired by support for STM32F4 SoC in the
usb_dc_dw driver (fce0b85eca).
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
The registers definitions will be needed when adding vendor-specific quirks
to this driver, so this commits moves them to a dedicated header file.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
API function:
- `pl011_irq_tx_enable` is expected to enable and trigger TX interrupt.
Due to HW limiation, PL011 won't trigger TX interrupt if some data
wasn't filled to TX FIFO at the beginning. So that `isr_cb` must be
called at first time to enable TX irq.
- `pl011_irq_tx_ready` will return true when FIFO can accept more
data. Here we don't need wait TX FIFO to be empty.
- `pl011_irq_tx_complete` will return true when all data have been
sent from the shift register.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Clean up occurrences of "#if IS_ENABLED(CONFIG_FOO)" an replace
with classical "#if defined(CONFIG_FOO)".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
When the uart is configured in non interrupt mode, then the mmio address
should be provided via DEVICE_MMIO_ROM_INIT.
Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
<soc.h> was included because some CMSIS helpers (__DMB/__ISB) were
needed. In ARM SoCs, inclusion of CMSIS headers depends mainly on how
HALs decide to do it, being usually an inefficient and fragile include
chain. Note that on ARM64 we're in a better position, as those are
defined in-tree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Old code only create one pl011 device instance though there are two or
more pl011 device defined in devicetree. This patch can fix this issue.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Create a driver specific configuration structure, containing the
required fields only. Since the config struct can now store a pointer to
the UART structure, casts from address to (struct pl011_regs *) are no
longer needed. PL011_REGS has also been dropped in favor of using the
config pointer directly now that it is possible.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Refactors all of the serial drivers to use a shared driver class
initialization priority configuration, CONFIG_SERIAL_INIT_PRIORITY, to
allow configuring serial drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The one
exception is uart_lpc11u6x.c which previously used
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS.
This change was motivated by an issue on the frdm_k64f board where the
serial driver was incorrectly initialized before the clock control
driver.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
ARM Server Base System Architecture defines Generic UART interface,
which is subset of PL011 UART.
Minimal SBSA UART implementation does not define UART hardware
configuration registers. Basically, only FIFOs and interrupt management
operation are defined.
Add SBSA mode to PL011 UART driver, so it can be used at SBSA-compatible
platforms, like Xen guest.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert older DT_INST_ macro use in arm_cmsdk/arm drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a fixed clock to the qemu-virt-a53.dtsi to match how the musca dts
files work so we get the clock DT info in the same way in the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In the DT_INST conversion we introduced a typo bug of accessing port0
instead of port1 in the IRQ config function.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The PrimeCell UART (PL011) IP can use one single combined/shared
interrupt line instead than different IRQ lines for TX/RX/Err/... This
is the most common configuration supported in the Linux world but not
currently supported in Zephyr. QEMU emulates a PL011 UART with a single
interrupt line as well.
To support this configuration we have to hookup the PL011 driver with a
shared IRQ driver and add two new configuration options when the shared
IRQ line is used.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The driver fails to compile when CONFIG_UART_INTERRUPT_DRIVEN=n. This is
due to a nested ifdef on CONFIG_UART_INTERRUPT_DRIVEN that is excluding
pieces of code unrelated to the uart interrupts management.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
