For a 16-bit data bus, "DT_INST_PROP_LEN(n, data_gpios)" returns 16
which is equals "MIPI_DBI_MAX_DATA_BUS_WIDTH(16)".
As a result, the assertion will always be triggered.
Use a "<=" condition for the assertion instead.
Signed-off-by: Hua Zheng <writeforever@foxmail.com>
Command "waitms 50" on ChromeBook EC console, then it will crash EC.
Because arch_busy_wait() is re-entried by two different tasks,
the second calling will reset the timer and may cause the first
calling to fail to reach the waiting destination
(if the first calling's wait time is longer enough).
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_error_case
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_monotonic
west build -p auto -b it8xxx2_evb tests/kernel/timer/starve
west build -p auto -b it8xxx2_evb tests/kernel/context
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Add empty function stubs to support building with the newly introduced
CONFIG_BUILD_ONLY_NO_BLOBS option.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The address passed in to the function was incorrect causing
failures when porting to RT1180.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
For the lists of properties passed as a pointer to the get_props and
set_props functions, there is no reason to not make the pointer const as
the called functions will not and should not alter the pointed-to data.
In practice, not having the pointers const can cause compilation errors
if trying to pass in a const array of properties.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@escolifesciences.com>
Use uint64_t instead of uint32_t for the FLASH_STM32_EX_OP_SECTOR_WP
extended operation.
Some chips have two banks, more than 16 sectors each e.g. stm32h7a3xx
chips, so more than 32 bits are required.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Fixed bug calculating offset of registers after unused space in the ADC
register space for the SZ package parts.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Avoid referring to Pico 2 (the name of a board). In this context,
RPI_PICO is used to refer to the (Zephyr) `SOC_FAMILY` rather than the
Pico 1 board. This clarifies common numerical values between the RP2040
and RP2350 SoC series, and enables existing DTS files to be used with
RP2350-based boards with fewer changes.
Remove the use of Zehpyr's `CONFIG_` macros from the device tree files,
and replace them with `SOC_SERIES`-specific files. Update the driver
implementation to conditionally include the correct file. Update
documentation and samples to match.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
The RP2350 SoC series contain two timer peripherals. Extend the driver
to support using the second timer (`TIMER1`).
N.b. this requires a fix from the Pico SDK to be patched into
hal_rpi_pico. See https://github.com/raspberrypi/pico-sdk/pull/1949 .
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
The watchdog register configuration of RP2350 differs from that
of RP2040, so we make fit that.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Unlike the RP2040, the RP2350 has multiple tick generators that need to
be started. Start TIMER0 and TIMER1 tick generators during
clock_control_init.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Extend the existing driver to add some initial support for the new SoC,
whilst maintaining compatibility with the RP2040.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
RP2350 is Raspberry Pi's newest SoC. From the datasheet:
"RP2350 is a new family of microcontrollers from Raspberry Pi that
offers significant enhancements over RP2040. Key features include:
• Dual Cortex-M33 or Hazard3 processors at 150 MHz
• 520 kB on-chip SRAM, in 10 independent banks
• 8 kB of one-time-programmable storage (OTP)
• Up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus
...
"
This commit introduces some changes to support the existing RP2040 and
what is describe by Raspberry Pi as the "RP2350 family". Currently there
are 4 published products in the family: RP2350A, RP2350B, RP2354A, and
RP2354A. Within Zephyr's taxonomy, split the configuration as follows:
Family: Raspberry Pi Pico. This contains all RP2XXX SoCs,
SoC Series: RP2040 and RP2350.
SoC: RP2040 and, for now, just the RP2350A, which is present on the Pico
2, where the A suffix indicates QFN-60 package type. This structure is
reflected in `soc/raspberrypi/soc.yml`, and somewhat assumes that there
won't be a RP2050, for example, as a RP2040 with more RAM.
This is foundation work ahead of introducing support for Raspberry Pi's
Pico 2 board, which is fitted with a RP2350A and 4MB of flash.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add support for SoC-specific clock ids and update the initialization
function to support the existing RP2040 and add support for the RP2350.
clock_control_rpi_pico.c uses numerical values for clock ids taken from
rpi_pico_clock.h which are the "clock generator". For the RP2350 these
values are different for some of the same logical clock sources, as well
as the RP2040 and RP2350 having different clock sources available.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
XIP prefetching seems to still be running, even while interrupts are
disabled. Therefore it is important to wait for the FlexSPI to be idle
before performing a write/erase operation.
Signed-off-by: Martin Stumpf <martin.stumpf@vected.de>
Add a GPIO driver for the Microchip MEC5 HAL based chips.
Current devices are: MEC174x, MEC175x, and HAL version of
MEC172x named MECH172x.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This adds initial support for NXP SDMA controller. We make use
of NXP HAL to configure the IP.
SDMA uses BD (buffer descriptors) to describe a transfer. We create
a cyclic list of descriptors and trigger them manually at start and
later when data is available.
This is tested using Sound Open Firmware app on top of Zephyr.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
- rename enable-gpios to en-gpios in adi,tmc2209
- place en-gpios in common stepper-controller.yaml
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
IRQ 1 is reserved for WiFi in ESP-IDF, which is used as the basis
for the Espressif HAL in Zephyr.
If IRQ 1 is used by Zephyr and too many other peripherals (e.g.
multiple UARTs) are enabled, WiFi stops working.
Marking IRQ 1 as "not available" seems to fix the issue.
Fixes#82874
Signed-off-by: Martin Jäger <martin@libre.solar>
The DHT[11/22] sensor driver fails to read data due to an extra
"gpio_pin_set_dt" that is occurs prior to waiting for the sensor active
response. This leads to consistent failed reads on esp32 (devkitc,
wrover). After removing this line reads are consistently successful.
Signed-off-by: Omar Naffaa <omarnaffaa.on@gmail.com>
Fast SPIM instances (SPIM120 and SPIM121) for correct operation require
the highest frequency from the global HSFLL. This commit adds needed
clock controller requests to the driver. When the runtime device power
management is enabled, the frequency is requested as long as the SPIM
is resumed, otherwise it is requested for the duration of transfers.
This commit also adds a missing call to `pm_device_runtime_put()` when
SPIM reconfiguration fails.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit fe0e2dbc60.
If `nrf_clock_control_request_sync()` ends up with a timeout, before
returning it must cancel the request that was not fulfilled on time.
Otherwise, the request may actually finish successfully a bit later,
but the caller will not be aware that the clock needs to be released
(since the call resulted in an error). And actually even more serious
problem is that because the `req` structure is placed on stack, after
the function returns, the contents of this structure will be probably
overwritten with some other data, so if the request finishes at that
point, an attempt to execute the callback function pointed by this
structure will most likely cause a crash.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
coverity complains of a missing break statement in SENSOR_CHAN_ALL case
this is fixed by adding __attribute__((fallthrough))
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The LoRa driver does not allow to pass void* user_data to callback in
lora_recv_async function. This leads to complex way of using the API. This
commit fixes the issue and adds the field to the function and to the
callback.
Signed-off-by: Aleksander Dejewski <aleksander.dejewski@gmail.com>
Rename "nxp,kinetis-ftm-pwm" compatible to "nxp,ftm-pwm" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Propagate bit ordering and type of CS pin to HAL layer. Previously,
the driver assumed MSB first and EUSART hardware CS control.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add nrf twis (I2C controller supporting I2C peripheral role and
EasyDMA) support, including updating the existing twis dt binding
to match the hardware with proper examples.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This patch adds support for HOST OpenThread communication to the RCP
co-processor via UART using SPINEL protocol.
The aim is to use OpenThread's RCP (Radio Co-Processor) with HOST device
(for example imxRT1020). Such configuration is the same as one used
with PC program (ot-cli) and RCP.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Implement the SPI context lock in the USART SPI driver for
EFM32/EFR32.
Remove incorrect -EBUSY error when spi_release() is called while
there are still bytes in the TX FIFO. This condition does not
cause the act of releasing the lock to fail.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Start and stop SAP, the IPv4 address is not removed, if then use STA
mode to connect to EXT-AP with same gateway address as the stopped
SAP, STA will not get the DHCP IPv4 address, as the DHCP offer packet
is dropped due to detect of IPv4 address conflict. Removing SAP IPv4
address when stopped SAP can fix this issue.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
apx needs to set compare b due to errata of XTAL glitch
ap4p needs to set minimum delta to 4
err026 requires XTAL to not be switched off/on when resetting
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Remove orphaned `k_mutex_unlock` in `eeprom_at25_read` as
the lock/unlock pair is handled in `eeprom_at2x_read` instead.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
To maintain consistency in `init_fn` parameter passing,
remove the address-of operator ('&') when assigning the `init_fn`
function pointer in the `DEVICE_DT_INST_DEFINE` macro.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Set up a named device MMIO memory mapping in the GPIO controller's
parent device, map the virtual memory in the init function of the
parent device.
Once the controller's register space has been successfully mapped,
propagate the mapped virtual address to all child (= GPIO bank)
devices. While it is possible to add a named mapping to every
single GPIO bank device and initialize it in the respective bank
device's init function, this would result in multiple virtual
address mappings all pointing to the same 4k of physical memory.
I assume that, although all those mappings having the same attri-
butes, such a setup is at least discouraged.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Return standard baudrate on a uart_config_get call instead of
rough calculated numbers.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Since now Mbed TLS automatically selects ENTROPY_GENERATOR (or the
test generator, depending on the platform) we can remove this dependency
from all BT related tests and samples.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Enable buffered write for nRF54l RRAM flash driver by default.
CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE=1 means that write will be buffered
by 16 B buffer (native RRAM write-bock-size).
This allows optimal life-endurance of RRAM memory.
For reference" DTS declares 16 write-block-size already.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
This patch fixes an assert in net_buf_simple_add() function when the
lan_9250 driver would add previously added data to the net buffer
on receiving large (>128 bytes) packat. This fix was to use the frags
field of the net_buf structure instead.
Tested with a nRF54L15 DK and eth3 click board (with nordic connect sdk
2.8.0 and this patch).
Signed-off-by: Balaji Srinivasan <balaji.srinivasan@autostoresystem.com>
Creation of the new zephyr\soc\nxp\common\nxp_nbu.c driver which manage
the interruption of the NBU. This modification is mandatory to support a
coex application which includes Bluetooth and 802.15.4 on the same
narrow band path.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
This commit Modifies the DMA STM32 Kconfig to enable shared IRQ
support for the STM32U0 series.
This change ensures DMA channels with shared IRQs are properly
configured for stm32u0 devices.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
The clock_stm32_ll_common.c function set_up_plls calls
LL_RCC_PLL_Disable();and it was not waiting for the
disable to complete before trying to configure
the pll sysclock which creates a race condition for
pll configuration.The wait for re-enabling the RCC pll
is already there, it was just missing the wait for
the disable before configuration. Also added the wait for PLL2.
Signed-off-by: Benjamin Curtis Byers <ben.byers@ubcobikes.com>
Adapt the stm32 flash driver for the stm32h7rs serie where some
bit of the FLASH registers are named differently from stm32h7 serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch will save configured link clock and ensure
ssp starts with xtal clock if ssp ver >= 2.0
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
First commit to add support for gpio interrupt on Renesas RA
- Add support for external interrupt driver
- Add support for gpio interrupt config
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
create rampstat Kconfig template to enable respective tmc drivers to
reuse the common configurations
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Convert vendor specific **_WIFI_BUILD_ONLY_MODE symbol as global
in order to provide common build flag to enable CI with no blobs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
ADS131M02 is Texas Instruments 2-channel, 24-Bit differential
input ADC which support wide range datarate.
Driver add support for adc read, channel configure, adc sampling
mode configuration and power management.
[1]. https://www.ti.com/lit/ds/symlink/ads131m02.pdf
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
config->base is already defined as ADC_TypeDef so no there is no need to
cast it as such. Remove all occurrences throughout the file.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that clock source and sequencer are defined with strings in device
tree, move the old defines directly in the driver
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that st,adc-sequencer and st,adc_clock-source use a string, update the
ADC driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
fu drv adc update driver with string
Remove specific cases for H7 and U5: group them together and only call a
single function. ADC3 of H72x/H73x and ADC4 of U5 are different from other
ADC of their series, and have dedicated functions in the LL for enabling
DMA, but they're doing the exact same operation as
LL_ADC_REG_SetDataTransferMode.
Incidentally, this change allows H7A/H7B to use the DMA (it seems to have
been missed before).
Last, this change enables the DMA support for F1x ADC.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32F3 and H7 have multiple ADC versions difficult to differentiate.
Use clearer macros to make code more readable.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use shell_device_get_binding() instead of device_get_binding() so that
we get the device based on its name and in addition by its label.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Mode 0 cannot establish a connection when used as a UDP server,
replace mode 0 with mode 2 to save the client's IP and port as
the communication address when a message is received.
Fixes#82898
Signed-off-by: Hongquan Li <hongquan.prog@gmail.com>
- Add "channel-available-mask" property in ADC node
to detect which channels are available to use
- Add "add-average-count" property in ADC node to chose
number of count of the addition or average mode
- Change the source code of ADC to match with 2 new properties.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The real, applicable and trusted values are the ones flashed into BICR.
So, drop DT properties that replicate BICR and use runtime reads to BICR
instead.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Rename everything from tla2021 to tla202x (except dtcompatible)
in preparation to add support for tla2022 and tla2024
Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>
Currently, there is a small race window where we can miss an interrupt.
Right after we're done reading the RX buffer but just before decrementing
the RX counter to zero, the ENC28J60 may receive a packet. The chip will
raise an interrupt, but the line is still asserted. That means that the
callback will not be invoked since it is edge-triggered.
To avoid that, disable interrupts on the chip itself before processing
the RX buffer.
In fact, the ENC28J60 datasheet specifically says:
"After an interrupt occurs, the host controller should
clear the global enable bit for the interrupt pin before
servicing the interrupt. Clearing the enable bit will
cause the interrupt pin to return to the non-asserted
state (high). Doing so will prevent the host controller
from missing a falling edge should another interrupt
occur while the immediate interrupt is being serviced.
After the interrupt has been serviced, the global enable
bit may be restored. If an interrupt event occurred while
the previous interrupt was being processed, the act of
resetting the global enable bit will cause a new falling
edge on the interrupt pin to occur."
This is also what is being done in the Linux driver [1].
[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1126
Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
The enc28j60 errata sheet says:
"The Receive Packet Pending Interrupt Flag
(EIR.PKTIF) does not reliably/accurately report
the status of pending packets."
"In the Interrupt Service Routine, if it is unknown if
a packet is pending and the source of the interrupt
is unknown, switch to Bank 1 and check the value
in EPKTCNT.
If polling to see if a packet is pending, check the
value in EPKTCNT."
A workaround has already been implemented inside of eth_enc28j60_rx().
But checking PKTIF before calling eth_enc28j60_rx() completely defeats
the purpose of the workaround. Do not check it.
Moreover, clearing ENC28J60_BIT_EIR_PKTIF is useless since it is
automatically cleared once all packets are read. So remove that check
and clarify comment.
Also please refer to the Linux driver [1].
[1] https://elixir.bootlin.com/linux/v6.11.2/source/drivers/net/ethernet/microchip/enc28j60.c#L1090
Signed-off-by: Xavier Ruppen <xruppen@gmail.com>
After a non-power reset (wdt) pins may remain in non-default state.
To ensure that a system initialization is the same after any reset,
it is necessary to initialize pins to the default state.
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
Map MMIO memory by using DEVICE_MMIO_NAMED_x() APIs.
And some platforms has no soc.h, so use __has_include to check it
firstly.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Mark the I2C instances as `PM_DEVICE_ISR_SAFE`, as the transition
operations are short, it saves RAM resources, and the spin-locking fixes
the non-atomic behaviour of the PM usage counter.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Enhance the driver to calculate the L2 cache line size and number
of ways at runtime. The L2 cache line size is assumed to match
the L1 cache line size, while the number of ways is determined
based on the total L2 cache size.
Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
Add max22190 gpio driver with input functionality, since device
support only input without output.
Implemented diagnostic functionality for all 8 channels
which include various check to over/under voltage and wire break.
Filtering configuration is done from devicetree on per channel
bases and is configured on chip start.
In case some fault condition occure FAULT pin drive LOW which
prop to FAULT registers to be read. Data is stored in data structure
for furter analizes and ERR message is printed in console.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Prepare to use official TDK Invensense Inc. driver for icm42670-P/-S
sensor in tdk_hal module. Simplify I2C and SPI transport files.
Driver code moves in hal_tdk module.
Adds APEX features, such as Pedometer, Tilt detection, Wake on Motion
and Significant Motion Detector.
Signed-off-by: Aurelie Fontaine <aurelie.fontaine@tdk.com>
find a sensor driver bug don't judge the data whether read back
correctly, deal with buffer data directly.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add a get_config function for this driver as specified in the
Ethernet subsystem API. The implementation supports querying
the hardware checksum generation capabilities of the specified
GEM device instance. This prevents the transmission of packages
without a valid checksum for protocols such as ICMP, as the
hardware only supports IPv4/IPv6 TCP and UDP checksum generation.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
There were redundant code in full_irq_lock(), full_irq_unlock()
functions that supposed to be used when ZLI IRQs are disabled.
These functions are compiled in only when CONFIG_ZERO_LATENCY_IRQS
is set, hence the non-ZLI execution path was never included
in final binaries.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This runs the Timer/counter in 'normal' PWM mode (for 8-bits)
and in 'match' PWM mode (for 16-bits).
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
Remove deprecated functions to comply with new HAL versions.
Handle capture interrupts more appropriately by clearing status
bit for only one channel.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
The dt_nodelabel_bool_prop must be used to check for a boolean property,
not the dt_nodelabel_has_prop. Using the latter caused the
UART_X_ENHANCED_POLL_OUT condition to be not fulfilled, despite the
fact that the property was not set on nRF52840 and nRF91.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
The assert BUILD_ASSERT(NRF_GPD_FAST_ACTIVE1 == 0); is not correct
given that NRF_GPD_FAST_ACTIVE1 is defined as 1U, and is not used
in the file anyway. Remove the build assert.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The nrf-hsfll was previously the only supported HSFLL clock, hence it
was not namespaced fully. Since we added nrf-hsfll-global, we should
add the namespace to nrf-hsfll as well.
Updates drivers and devicetree uses of HSFLL as well.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Conditionally compile in controller features based on what features
have been enabled in Kconfig
This commit allow saving in flash size. Over 10k in peripheral_hr
and central_hr. In observer and broadcaster about 20k
Signed-off-by: Petri Pitkanen <petri.pitkanen@silabs.com>
With changes introduced in commit 6a3602a306
("net: buf: Clear `user_data` on allocation")
our memset() calls are redundant.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
When the CONFIG_BT_STM32WBA the stm32wba_fm flash driver is compiled
and must takes flash_stm32_sem_take/give functions from the
flash_stm32.h header file, like other stm32 series.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add two new flash extended operations for reading and writing STM32
option bytes from the application code.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Default enable WIFI_NM for both supplicant and embedded supplicant
case, to distinguish STA and SAP interface when use L2 layer.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
These device driver APIs were merged after the DEVICE_API macro was
introduced.
Cleanup these leftover drivers.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The clock controller/manager registers are updated with
the correct divider values by bootloader via hand-off
data, so now we can use the clock controller to get the
clock value of each peripheral during the run time.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Prevent the driver from perfroming transfer when SPI_LINES_OCTAL flag
is specified, as this driver supports only SPI_LINES_DUAL for now.
Signed-off-by: Michal Morsisko <morsisko@gmail.com>
Add support for sending and receiving the least significant bit first
for the spi_bitbang driver. This driver can now be used with
SPI_TRANFER_LSB flag.
Signed-off-by: Michal Morsisko <morsisko@gmail.com>
The actual clock speed of the bus is partially determined by the
rising/falling edges of the SCL. These settings allow applications
to tune the clock based on board characteristics.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Enable the device runtime power management on the SPIM shim.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Kconfig names follow the convention CONFIG_I2C_driver-name. Rename
RENESAS_RA_I2C_IIC to I2C_RENESAS_RA_IIC to align this config name
with all others.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Originally, when the timer's source clock is 32.768 kHz, the timer driver
uses two consecutive reads to ensure the timer reading is correct.
However, it is not robust enough due to an asynchronous timing issue in
the chip. The workaround is to add at least two NOPs between the
LDR and CMP instructions. This commit implements the workaround in the
assembly code to ensure it is not affected by the compiler toolchain
or optimization flags.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit aims to improve the integration of `esp_wifi_drv` by
providing the link mode information to `wifi_mgmt` when a station device
is connected to the AP.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Compilation will fail if multiple models are used at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Use HEAP_MEM_POOL_ADD_SIZE_ to add heap for NXP Wi-Fi. For supplicant
case, define less heap, as CONFIG_HEAP_MEM_POOL_ADD_SIZE_HOSTAP and
CONFIG_HEAP_MEM_POOL_ADD_SIZE_SOCKETPAIR are also enabled.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
Set TWT response parameters to zero to avoid
uninitialized values and ensure correct behavior.
Signed-off-by: Triveni Danda <triveni.danda@nordicsemi.no>
Currently, MT25 flashes were running in 3-byte mode.
This is not compatible with the chip we use in our project (MT25QU01GBBB),
as only 128 Mbit of its 1 Gbit can be addressed.
Signed-off-by: Martin Stumpf <finomnis@gmail.com>
To facilitate changing this driver, decouple rtio from functions not
specific to RTIO. This also requires moving the sdk driver handle
creation outside of the configure call. An effect of this is we can
stop initializing an unused sdk driver handle for the dma path.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
These changes:
* Fix the check of the word size to be more useful
- check min frame size instead of max
- check for min word size requirement
- add a clarifying comment about what the word size represents in
hardware since the nomenclature from zephyr does not match the nxp
references
* Add a clarifying comment about half duplex being supported by hardware
* Add LPSPI_ namespace to defines
* Change chip select error message to be more clear about the problem
* Move the check of the clock device being ready to the lpspi init,
instead of checking it every time on configure. It probably also makes
more sense to not ready the lpspi device if the clock is not ready.
* Move the bare-metal configuration of bit fields AFTER the SDK Init
call.
* Return the proper error code if clock control call errors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Compilation will fail if both adin2111 and adin1100 are used
at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Resets uart tx fifo during driver initialization to have a well defined
initial condition mainly preventing unwanted characters being sent
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
No need for an extra step to enable feature in the driver as it clearly
depends on the supplicant feature.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source
Requires to identify the PLL source HSE or HSI.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the configuration of the PLL Q divider of main PLL
and I2S_Q of the PLLI2S toset the PLL48MHz clock which feeds
the USB, SDMMC, RNG through the RCC_DCKCFGR2 register.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Make sure that channels are inactive before releasing them.
This way, there won't be any leftover interrupts needed to be
handled when disabling IRQs.
This patch introduces a new state: CHAN_STATE_RELEASING. This is mostly
useful for the per-channel PD support in which the ISR needs to check
that the channel PD is enabled before attempting to access its register
space.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Commit 48b98a9284 ("drivers: dma: dma_nxp_edma: disable IRQs when
not needed") moved the IRQ enable operation to edma_start() and added
an IRQ disable operation in edma_stop(). This is wrong because it breaks
the DMA API contract w.r.t dma_start() being `isr-ok` on imx8qm/imx8qxp.
As such, move the IRQ enable and disable operations in
dma_request_channel() and dma_release_channel().
Note1: managing the interrupts like this is only really needed when
dealing with interrupt controllers that have a power domain associated
with it (which is the case for irqstr on imx8qm/imx8qxp).
Note2: Zephyr has no reference count for shared interrupts so disabling
a shared interrupt without checking if someone else is using it is
dangerous.
Based on the aforementioned notes, the irq_disable() operation is only
performed if irqstr is used as an interrupt controller (which is only
the case for imx8qm/imx8qxp). Otherwise, the operation isn't needed.
Fixes#80573.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The channel state transitions are currently performed at the
beginning of each of the functions that triggers them
(e.g: edma_start(), edma_stop(), etc...). The main issue with
this approach is the fact if there's any failures after the state
transition then the channel will be in the target state without
performing the required steps for it.
For instance, during edma_config(), if any of the functions after
the state transition (the channel_change_state() call) fails
(e.g: get_transfer_type()) fails then the state of the channel
will be CONFIGURED even if not all the required steps were performed
(e.g: setting the MUX, configuring the transfer, etc...).
To fix this, split the state transition into two steps:
1) Check if the transition is possible.
2) Do the transition.
First step should be done before any configurations to make sure
that we should be performing them in the first place, while the
second step should be performed after all configurations, thus
guaranteeing that all the required steps for the target state were
performed before transitioning to it.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The Microchip CAP12xx series are available in 3, 6 or 8 channel versions.
Co-authored-by: Benjamin Cabé <kartben@gmail.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Implement the zero latency interrupt safe APIs to the HFXO clock
commonly used by the bluetooth stach from zero latency interrupt
context.
Co-authored-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Adds driver support for the charge enable (ce) gpio. This GPIO is
optional and if no GPIO is allocated the pin is assumed to be asserted.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
The ADC_ADS1X1X_TRIGGER macro was defined without an explicit value,
preventing ALERT/RDY pin configuration even when alert_rdy_gpios
were properly defined in devicetree. This occurred because
the IF_ENABLED macro specifically requires macros to be defined as 1,
not just defined empty.
Fixed this by explicitly defining ADC_ADS1X1X_TRIGGER as 1 when
alert_rdy_gpios properties are present in devicetree.
Signed-off-by: Benjamin Geiger <BenjaminGeiger1@gmail.com>
This commit fixes a shared context between multiple instances of the
INA230 and INA236 driver. The issue is the naming of the instance data in
`INA230_DRIVER_INIT` macro when we have one instance of INA230 and one
of INA236 the name of the data variable will be `drv_data_0`. This
variable will then be passed to both instances.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
Add a driver for the Nintendo Nunchuk, accessed through the I2C bus.
This driver only supports the joystick and the buttons, not the
accelerometer.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Do not allow enqueuing buffers on endpoints that were not enabled. Doing
so can lead to division by zero later on because the max packet size can
be 0 in disabled endpoint configuration.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
It may be required to get information if NRF LF clock control calibration
is in progress. Some time sensitive operations could benefit from this
information.
The commit adds simple function that provides the information.
The function is nRF platform specific.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
VPR address was obtained from the child instance, however, the child
nodes address is purely an index within the VPR node. The VPR address
needs to be obtained from the parent.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update init function so APPCPU could not altere the clock setup.
Fix build in case if no inter-cpu module is selected.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This is the initial commit to support UART driver for Renesas RZ/G3S.
The driver only implements polling API for minimal support.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit introduces support for the I3C driver on STM32, enabling
functionality APIs for I3C controllers.
Signed-off-by: Mohammad Badawi <zephyr@exalt.ps>
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Add set_ctrl function API for vertical and horizontal flip control
modifying the camera read mode
Signed-off-by: Jeronimo Agullo <jeronimoagullo97@gmail.com>
Raise the poll signal when the socket is being closed to prevent users
of `zsock_poll` blocking after the socket is no more.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add cancel action wait ops to cancel remain on channel after TX on
specific channel, in case we need to remain on another channel later.
Signed-off-by: Fengming Ye <frank.ye@nxp.com>
LJ packages have 16 ADC channels vs 8 for SZ packages. Enhance
devicetree to account for this as well as conditional defines/code.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
This patch refactors the power management initialization for the Intel
ADSP GPDMA driver. The changes include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the `intel_adsp_gpdma_init`
function.
2. Ensuring that the GPDMA driver is initialized with the appropriate
power management state and that runtime power management is
automatically enabled based on the device tree configuration.
These changes streamline the power management initialization process and
ensure consistency with other drivers.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch refactors the power management initialization for the SSP
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the `ssp_init` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the SSP nodes
in the device tree files for ACE15, ACE20, and ACE30.
3. Moving the power domain assignment for the SSP device in the device
tree. The previous configuration resulted in the device not being under
any power domain and being initialized as always ON.
These changes ensure that the SSP driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch refactors the power management initialization for the DMIC
driver across ACE15, ACE20, and ACE30 generations to align with the
recommended practices outlined in the documentation. The changes
include:
1. Replacing the conditional initialization of power management state
with a call to `pm_device_driver_init` in the
`dai_dmic_initialize_device` function.
2. Adding the `zephyr,pm-device-runtime-auto` property to the DMIC nodes
in the device tree files for ACE15, ACE20, and ACE30.
These changes ensure that the DMIC driver is initialized with the
appropriate power management state and that runtime power management is
automatically enabled based on the device tree configuration. The
functionality of the power management state remains unchanged, ensuring
consistent behavior.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses the issue of invalid initialization sequence and
the use of registers in `dma_config` before the device is fully
initialized in the Intel ADSP HDA DMA driver.
Changes include:
1. Moving the `intel_adsp_hda_channels_init` call to the
`intel_adsp_hda_dma_init` function to ensure that channels are
initialized during device initialization.
2. Removing the redundant call to `intel_adsp_hda_channels_init` from
the `PM_DEVICE_ACTION_RESUME` case in the
`intel_adsp_hda_dma_pm_action` function.
These changes ensure that the device and its channels are properly
initialized before any DMA configuration is performed, preventing access
to hardware registers before the device is ready.
**Note:** This is a proposed solution, and a different approach should
be considered. Currently, we are accessing registers before the device
and power domain are fully powered up. This solution likely works
because the DMA is used to load firmware during the boot process, and
the necessary power domains are already powered up. Further
investigation and a more robust solution are recommended to ensure
proper initialization and power management.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses several issues with the Intel ADSP HDA DMA driver:
1. Refactors the HDA DMA power management initialization. The previous
use of `pm_device_runtime_enable` was incorrect. The updated approach
relies on enabling runtime power management through the device tree
using the `zephyr,pm-device-runtime-auto` property. Additionally, the
patch removes redundant device initialization steps as these are already
handled by `pm_device_driver_init` when the device is under a power
domain.
2. Corrects the power domain assignment for the HDA link. The HDA link
was previously assigned to the io0 power domain based on a
misinterpretation of the documentation. The correct power domain
assignment is now based on updated documentation for LNL, ensuring that
the HDA link is associated with the appropriate power domain.
These changes ensure that the HDA DMA driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the correct power domains are used.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch addresses the following issues with the Intel HDA DAI driver:
1. Adds power management support for the HDA DAI driver by implementing
the `hda_pm_action` function and integrating it with the Zephyr power
management framework.
2. Ensures balanced calls to `pm_device_runtime_get` and
`pm_device_runtime_put` by modifying the `probe` and `remove`
functions to use these power management calls.
3. Ensures that the io0 power domain is active when the HD Audio is in
use by assigning the correct power domain to the HDA DAI devices in
the device tree files for various Intel ADSP platforms (ace15_mtpm,
ace20_lnl, ace30, ace30_ptl).
4. Enables runtime power management for the HDA DAI devices by adding
the `zephyr,pm-device-runtime-auto` property in the device tree.
These changes ensure that the HDA DAI driver properly manages power
states, reducing power consumption and improving system stability, while
ensuring the io0 power domain is active when required.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Compilation will fail if multiple models are used at the same time.
Changing to define different unique names for the symbols
to avoid conflicts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The lsm6dso driver does not correctly reflect the status of
the node in dt. So the driver didn't compile even if
`st,lsm6dso32` node exists.
I fixed it to correctly go through ithe compile.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Use the mipi_dbi_configure_te API within the st7796s display driver.
If the MIPI DBI controller supports the tearing enable signal, then
configure the ST7796S to output the TE line signal.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for the mipi_dbi_configure_te API within the NXP LCDIC
peripheral. Also, remove a redundant code patch in the write_command
function that was previously used to determine when the display driver
was writing to graphics RAM, as these writes should now be performed
using the mipi_dbi_write_display API.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename "nxp,kinetis-lpuart" compatible to "nxp,lpuart" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce new binding "st,stm32u5-otghs-phy" for OTG_HS PHY. This allows to
configure clock source and handle STM32U5 specific OTG_HS PHY behavior in
driver implementation in a more readable way.
Move OTG_HS PHY clock selection (previously <&rcc STM32_SRC_HSI48
ICKLK_SEL(0)>) from OTG_HS node to OTG_HS PHY node.
Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5
CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
Support enabling OTG_HS PHY clock, which is bit 15 (OTGHSPHYEN) in
RCC_AHB2ENR1. Change OTG_HS clock to be bit 14 (OTGEN).
Calculate in runtime OTG_HS PHY clock source frequency. Try to match that
to supported (16, 19.2, 20, 24, 26, 32 MHz) frequencies and select proper
option with HAL_SYSCFG_SetOTGPHYReferenceClockSelection() API (instead of
hardcoded 16 MHz selection).
Co-authored-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Support specifying divided clock buses by introduction of
STM32_CLOCK_DIV(div) macro. This macro can be used in devicetree to define
clock source of peripherals.
HSE is selected in devicetree using:
<&rcc STM32_SRC_HSE ...>;
HSE/2 can now be selected with:
<&rcc (STM32_SRC_HSE | STM32_CLOCK_DIV(2)) ...>;
This allows to use clock_control_get_rate() API in peripherals in order to
get desired clock rate.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
in the switch case in the preceeding for loop if default path is taken
all the time, then the ret variable will stay uninitialized, the original
contributor of this driver has provided a comment that this path shall
never be reached, however, it is better to return an error code instead
of continuing with an incorrect configuration, hence this commit replaces
continue with a proper return errno.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
for the brevity renaming direction_gpios to dir_gpios since STEP/DIR
interface is quite an established term in context of stepper controllers.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The current implementation of tmc2209 driver does not allow instantiation
of the driver without configuring msx pins.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The SD physical layer specification requires that the operating supply
be stable for at least 1 millisecond before providing the required 74
clocks. The maximum VDD ramp time is specified at 35ms, giving a total
minimum delay of 36ms.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This PR fixes a blocking call to video_buffer_alloc in case of memory
shortage by addign a timeout parameter to the API.
Signed-off-by: Armin Kessler <ake@espros.com>
Added support for SPI in 4-wire and 3-wire configurations to
the Infineon AIROC WiFi driver (drivers/wifi/infineon).
Review changes:
Move DT_DRV_COMPAT to common header file
Correct board-specific preprocessor lines
Removed AIROC_MAP_COUNTRY_CODE
Move Pico W configuration details to devicetree
Use pinctrl to manage shared data/interrupt GPIO
Clean up bus selection in Kconfig.airoc
Make SDIO and SPI bus struct independent
Replace LOG_DBG with LOG_ERR
Remove functionally duplicate operation
Remove spurious Kconfig option
Minor cleanup in CMakeLists.txt
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
This PR adds support for LAN9250 spi ethernet controller.
This driver is tested on the Mikroe ETH Click 3
https://www.mikroe.com/eth-3-click
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add support for optimized short log messages (aka turbo logs). They are
supported on cpuapp and co-processors owned by cpuapp (FLPR and PPR).
In general, it can be supported if cpuapp has access to logging strings
used for the log message. Currently mode is supported only in standalone
logging. When it is extended for dictionary logging then it will also
be supported on other cores (e.g. cpurad).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
entropy_nrf5 modules uses k_sem_xxx() functions in several
places, but these functions are only functional when
CONFIG_MULTITHREADING is set, otherwise they just fallback to
the empty weak implementation provided in
zephyr/lib/libc/armstdc/src/threading_weak.c.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
mcux_rnga driver calls k_cycle_get_32() which is not available
if CONFIG_SYS_CLOCK_EXISTS is not defined. Therefore we add
this depedendency to CONFIG_ENTROPY_MCUX_RNGA.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Automatically enable ENTROPY_GENERATOR if the device-tree has
any "zephyr,entropy" chosen property specified. This helps
in having CONFIG_ENTROPY_HAS_DRIVER set if the platform support
an entropy driver and this then enables CONFIG_CSPRNG_ENABLED.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Now that we enable `HAS_BT_CTLR` we should also declare which optional
features are supported. For now, we only add the features that are
available through the current driver init routine and found on all
supported platforms.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The tcpc_get_status_register function was using int32_t for the status
parameter, while the other related functions used uint32_t. This change
unifies the data type across all related functions to uint32_t for
consistency and clarity.
Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
When fast UARTE instance is used (e.g. UARTE120 in nrf54h20), PM actions
are not ISR safe because they include communication over IPC so they can
only be called from the thread context. Extend driver to support both
PM modes. When non ISR mode is used then uart_rx_enable() and uart_tx()
will return error if they are called from ISR and resume operation
would need to be called because device is suspended. On completion,
driver is calling pm_device_runtime_put_async which can be called from
the ISR context.
Additionally, suspending in the TXSTOPPED and RXTO events has been
moved after user callback. It allows to support the case where
uart_rx_enable() or uart_tx() are called from that callback context.
Since suspending is called after returning from the callback it will
not trigger suspend action because API called in the callback context
will increment the usage counter (when pm_device_runtime_get() is
called).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Extends the MIPI DBI SPI driver class for operating mode C4, SPI 4-wire,
with 16 write clocks to send one or multiple byte for commands. Generic
data (e.g. GRAM) aligned to 16-bit are passed through and stuffed with
bytes if required.
Signed-off-by: Stephan Linz <linz@li-pro.net>
The more complex the SPI transfer algorithms become, the more
confusing the current implementation of the SPI write function
becomes. Furthermore, if further as yet unknown MIPI DBI modes
are to be supported, the scope of this implementation would
increase dramatically. With the splitting now introduced, the
existing SPI transfer algorithms are moved to individual
auxiliary functions and the SPI write function only focus on
the decision of the respective MIPI DBI mode and the device
lock/unlock.
Signed-off-by: Stephan Linz <linz@li-pro.net>
The more complex the SPI transfer algorithms become, the more
confusing the current implementation of the SPI command read
function becomes. Furthermore, if further as yet unknown MIPI
DBI modes are to be supported, the scope of this implementation
would increase dramatically. With the splitting now introduced,
the existing SPI transfer algorithms are moved to individual
auxiliary functions and the SPI read function only focus on
the decision of the respective MIPI DBI mode and the device
lock/unlock.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Implement the readout protection for the STM32H7 series.
Define the specific functions used by the flash_stm32h7.
Move the stm32h7 flash register manipulation in a write_optb()
to be called by the flash_stm32_set_rdp_level.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Place the flash_stm32_sem_take and flash_stm32_sem_give
function to header file for common to use in any flash driver
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Check the return value of gpio_add_callback() in the display init
function, to resolve an issue flagged by static analysis.
Fixes#81921
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
"wlen" variable set to return value of mipi_dsi_transfer should be a
ssize_t type, so that if a negative value is returned the error will be
caught and returned.
Fixes#81929
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix dead code within the set_pixel_format() function for the RM67162.
This function should set the relevant data fields for the driver, then
send the MIPI DCS command to change pixel format.
Fixes#81945
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
BLE public address assignment shall be done only when
CONFIG_BT_HCI_RAW is not enabled.
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
On the interrupt handling, one thread per driver instance is involved
into monitoring the semaphor, sends inside the gpio callback triggered
by the gpio interrupt. Each time, when the link parameters are change,
the DM8806 is generating the gpio interrupt. After getting semaphor,
the application callback function which was linked during initialization
process is called to get the new link parameters with standard API
calls
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
New driver for Davicom DM8806 PHY. Driver is using standar mdio API
to manage the DM8806 switch controller. Register access needs the
PHY addres or switch address to be one of five possible values, since
DM8806 has built-in five PHY's. These values should be defined in the
application .dts file. One DM8806 ethernet port must corresponds with
one ethernet PHY node with two properties for ethernet port: one for
PHY address and one for switch address - <reg> for register access from
Internal PHY Register area and <reg-switch> for register access from
Switch Per-Port Registers area. Device tree example below:
example device-tree:
dm8806_phy: ethernet-phy@0 {
reg = <2>;
reg-switch = <8>;
compatible = "davicom,dm8806-phy";
status = "okay";
davicom,interface-type = "rmii";
reset-gpio = <&gpiod 2 GPIO_ACTIVE_LOW>;
interrupt-gpio = <&gpioc 1 GPIO_ACTIVE_HIGH>;
};
Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
Adds a step direction binding that can be used with any stepper that
implements said control interface to cut down on boilerplate code.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
There were code paths that could have lead to divide by zero given an
invalid scale setting for accel or gyro. In practice this should be an
invalid setup even before getting to these conversion functions. The
conversion functions now better show all valid values are accounted for
by using CODE_UNREACHABLE in the default case.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Now that the U5 HAL contains the dedicated LDO status function, use it
instead of reading the register directly.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
New HAL update changed the prototype of the check DMA flag functions.
H7 and U0 use a const parameter for these functions.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
On NXP RT1170 SOC, ADC ETC exists but it can not be enabled because
of dependency on HAS_MCUX_ADC_ETC.
Also, ADC ETC should only work with ADC together, there is no use
case to run it standalone.
Fixes:#81466
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
If CONFIG_SPI_STATS is enabled, the device state for all SPI controller
drivers must contain the SPI stats. This space is allocated by calling
Z_SPI_INIT_FN as part of the device definition; this is done automatically
when using SPI_DEVICE_DT_DEFINE instead of DEVICE_DT_DEFINE. If space for
statistics is not properly allocated but CONFIG_SPI_STATS is enabled, an
unexpected write to memory outside of the stats region may occur on a SPI
transfer. This commit uses SPI_DEVICE_DT_DEFINE or
SPI_DEVICE_DT_INST_DEFINE for all in-tree SPI controller drivers.
Signed-off-by: Dane Wagner <dane.wagner@gmail.com>
Rename "nxp,kinetis-dspi" compatible to "nxp,dspi" to remove the
device family from its name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The FlexSPI NOR driver should verify all 3 bytes of the JEDEC ID match
the expected value before attempting to use a custom LUT table with a
flash chip. This reduces the odds that an incompatible LUT will be used
with a flash chip, as some flash chips may share the same first byte of
their device ID but not be compatible with the custom LUT table.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The controller behind the EFR32 driver is a local link layer
implementation, so it makes sense to select HAS_BT_CTLR.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
On RT1180/RT700, there is no gpr register on soc,
so change driver to get configuration register base
address from dts, instead of hard code.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Deprecate mode which is using TIMER+(D)PPI for reliable byte counting.
Recently a new approach is added (CONFIG_UART_NRFX_UARTE_ENHANCED_RX)
which supports reliable byte counting without additional HW resource.
This mode is planned to be the only supported RX path mode.
Enhanced RX has slightly different behavior. There are no partial RX
packets (events with non-zero offset). There is UART_RX_BUF_RELEASED
after each UART_RX_RDY event.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Due to clock designed on RT1180 has some different with other platforms,
so add macro and handle the clock difference in mcux_ccm_get_subsys_rate.
TPM1 use Bus_Aon as clock root.
TPM3 use Bus_Wakeup as clock root.
Other instances have independent clock root.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
