Add comment to DTS file about SRAM partitions similar to the RTXXX
series has comments.
Add also a doc section to the frdm_rw612 about this.
Also fix the section hierarchy of the frdm_rw612 doc, the header levels
were wrong since the wifi and bluetooth, and reference sections were
under the debugging section.
Group all the wireless connectivity info together.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for the Antmicro's Myra SiP Baseboard. The board uses
Antmicro's Myra SiP which integrates STM32G491XX MCU and its SoC
configuration.
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `smb-wui` property to support wake-up from sleep mode by START
condition when i2c is configured to target mode.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This adds support PWM EMIOS for NXP S32Z SoC, both PWM pulse
generate and pulse capture are supported
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/xspi@47001400: node name
for SPI buses should be 'spi'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/octospi@52005000: node name
for SPI buses should be 'spi'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the CMake Warning on build/zephyr/zephyr.dts:
Warning (spi_bus_bridge): /soc/octospi@52005000: node name
for SPI buses should be 'spi'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add initial SoC support for the TI J722s SoC series MCU-domain
Cortex-R5 core.
TRM for J722s: https://www.ti.com/lit/zip/sprujb3
Signed-off-by: Andrew Davis <afd@ti.com>
Add initial SoC support for the TI J722s SoC series MAIN-domain
Cortex-R5 core.
TRM for J722s: https://www.ti.com/lit/zip/sprujb3
Signed-off-by: Andrew Davis <afd@ti.com>
This commit adds MBOX device tree entry for MCXN947.
Adds support for MCXN in NXP ipm and mbox drivers.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Move the Atmel SAM E70/V71 DMA PERIDs header file to
include/zephyr/dt-bindings/dma and unify it for use with the entire product
family (SAM E70/S70/V70/V71).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Synchronize the Atmel SAM E70/V71 DMA Peripheral Hardware Requests HW
Interface Numbers and adjust them to match those listed in the SAM
E70/S70/V70/V71 datasheet.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Sort the Atmel SAMx7x periheral devicetree nodes according to their address
in the memory map.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and
MCLK. The old devices had defined the peripheral clock enable bit at PM.
On the newer devices this was extracted on a dedicated memory section
called Master Clock (MCLK). This change excludes the dedicated bindings
in favor of a generic approach that cover all cases.
Now the clocks properties is complemented by the atmel,assigned-clocks
property. It gives the liberty to user to customize the clock source
from a generic clock or configure the direct connections.
All peripherals drivers were reworked with the newer solution.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Relocate the `power-states` node from under the `soc` node to
the `cpus` node, making it consistent with other STM32 SoC series.
This resolves the device-tree warning:
(simple_bus_reg): /soc/power-states: missing or empty reg/ranges property.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
TIM8 was missing from the dts board file. This is one of the
advandaced-control timers on the STM32H562xx/STM32H563xx processors.
Signed-off-by: Omeed Baboli <omeedbaboli@gmail.com>
- Add Flash HP support for ra6-cm4, ra6-cm33, ra4-cm33 (except
r7fa4w1ad2cng)
- Add config to set the minimal size of data which can be written
for RA4E2, RA4M2, RA4M3, RA6E1, RA6E2, RA6M1, RA6M2, RA6M3, RA6M4,
RA6M5
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
- Bring macro defined of RA8 in flash_hp_ra.h to device tree
- Change to use irq_lock instead of semaphore for code flash
- Modify and add conditions to check and make decision to perform
action at last block.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
After updating the "st,stm32-vref" binding with a new property containing
the calibration data resolution ("vrefint-cal-resolution"), update the
corresponding nodes in SoC DTSI files with the proper value.
Note that the property is not set on SoCs with resolution of 12, as it is
the default value specified for the property in the binding.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Refactor the devicetree files for the Atmel SAM E70 and SAM V71 product
series. These SoCs are part of a larger product family (SAM
E70/S70/V70/V71) and share a common set of peripherals.
Introduce a base samx7x.dtsi for all members of the family, containing the
union of all supported peripherals. Specific product series can use
/delete-node/ in their DTSI (e.g. same70.dtsi) for removing peripherals not
present in that product series.
Replace pin-count-specific DTSI files (e.g. same70q19b.dtsi) with
pin-count-agnostic DTSI files (e.g. same70x19b.dtsi) as the pin-count is
not taken into account in these anyways, and adjust the relevant board
devicetrees accordingly.
As part of this refactoring, introduce support for the missing flash memory
density variants of the SAM E70 product series.
Support for the two remaining product series (SAM S70/V70) is not part of
this refactoring as these will require further changes to the SoC support
code (soc/atmel/sam/).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
